Dept. of Electrical Engg., IIT Madras
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- C. Bheemisetti et al. "A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver." IEEE Journal of Solid-State Circuits (2024).
- A. K. Unnam, P. Banerjee and N. Krishnapura, "An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS," IEEE Solid-State Circuits Letters, doi: 10.1109/LSSC.2024.3412634.
- A. Narayanan, A. Bhat and N. Krishnapura, "A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays," IEEE Journal of Solid-State Circuits, Accepted. (doi: 10.1109/JSSC.2024.3373620.)
- P. Kumar and N. Krishnapura, "Signal-Strength Detector Based on CMOS-Inverter Supply Current," IEEE Solid-State Circuits Letters, vol. 6, pp. 237-240, 2023. doi: 10.1109/LSSC.2023.3307361.
- R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, (doi: 10.1109/JSSC.2022.3171790.)
- Nagendra Krishnapura, "Analysis of Signal Transmission through Time-Varying Inductively Coupled Links," 2024 International Symposium on Circuits and Systems(ISCAS), Singapore, May 2024.
- A. Narayanan and N. Krishnapura, "Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs," 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, 2023, pp. 1-5.
- Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, and Nagendra Krishnapura, "A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India. (Co-recipient of the best paper award).
- Sumit Kumar and Nagendra Krishnapura, "Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India.
- Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura, "Bandpass filter and oscillator ICs with THD < -140dBc at 10Vppd for testing high-resolution ADCs," 2023 International Solid-State Circuits Conference, San Francisco, USA, Feb. 2023. doi: 10.1109/ISSCC42615.2023.10067771.
- R. S. Ashwin Kumar and Nagendra Krishnapura, "Multi-channel Delta-Sigma Analog-to-Digital Converters Without Reset," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India.
- Shanthi Pavan and Nagendra Krishnapura, "Linear Periodically Time-Varying Systems: Analysis and Applications," IEEE International Symposium on Circuits and Systems, 21-25 May 2023, Monterey, California, USA.
- Saurabh Saxena and Nagendra Krishnapura, "Architecture and circuits for fractional-N clock synthesis in wireline/wireless applications," Full Day Tutorial at the 32nd International Conference on VLSI Design, 5-9 January 2019, New Delhi, India.
- Saurabh Saxena and Nagendra Krishnapura, "High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery," Full Day Tutorial at the 31st International
Conference on VLSI Design, 6-10 January 2018, Pune, India.
- Shanthi Pavan and Nagendra Krishnapura, "Demystifying Time-Varying Systems," Half Day Tutorial at the 27th International Conference on VLSI Design, 4-8 January 2016, Kolkata, India.
- N. Krishnapura, "Pedagogy of Negative Feedback Circuits," Half Day Tutorial at the 27th International
Conference on VLSI Design, 5-9 January 2014, Mumbai, India. (abstract)
- N. Krishnapura and S. Pavan, "Negative Feedback System and
Circuit Design," Full Day Tutorial at the 22nd International
Conference on VLSI Design, 5-9 January 2009, New Delhi, India. (abstract, Lecture and notes)
- N. Krishnapura and S. Pavan, "Oversampling Analog to Digital
Converters," Full Day Tutorial at the 21st International Conference
on VLSI Design, 4-8 January 2008, Hyderabad, India. (abstract, Lecture
and notes)
- Nagendra Krishnapura and Pranav Kumar, "A signal strength indicator circuit," Indian patent 545473, 22 July 2024.
- Chithra and Nagendra Krishnapura, "DLL and method for auto-zeroing static phase offset," Indian Patent 501606, 22 January 2024.
- Ashwin Kumar R. S. and Nagendra Krishnapura, "Multi-channel ADC realization using a delta-sigma modulator without reset and a modulated-sinc-sum filter," Indian Patent 487682, 22 December 2023.
- Abhishek Bhat and Nagendra Krishnapura, "Phase error measurement circuit with referenceless gain and offset calibration," Indian Patent 487682, 22 December 2023.
- Madhukar Vallabhaneni and Nagendra Krishnapura, "A method of producing a linear current signal in a baseband Voltage-to-Current(V-I) converter," Indian Patent 481665, 13 December 2023.
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Nagendra Krishnapura and Rakshitdatta K. S., "Method for determining distortion contribution of individual elements of a circuit," Indian Patent 375099, Aug. 23, 2021.
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I. Shpantzer, M. Tseytlin, Y. Achiam, A. Salamon, I. Smilanski,
O. Ritterbush, P. S. Cho, L. Guoliang, J. Khurgin, Y. Meiman,
A. Demir, P. Feldmann, P. Kinget, N. Krishnapura, J. Roychowdhury,
J. Schwarzwalder, C. Sciabarra, "System and method for code division
multiplexed optical communication," US 7,167,651,
Jan. 23, 2007.
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I. Shpantzer, Y. Meiman, M. Tseytlin, O. Ritterbush, A. Salamon,
P. Feldmann, A. Demir, P. Kinget, N. Krishnapura, J. Roychowdhury,
"System and method for orthogonal frequency division multiplexed
optical communication," US 7,076,169, Jul. 11, 2006.
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N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,816,003, Nov. 9, 2004.
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N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,717,461, Apr. 6, 2004.
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N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,683,492, Jan. 27, 2004.
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P. Kinget and N. Krishnapura, "Glitch Free Phase Switching
Synthesizer," US 6,671,341,
Dec. 30, 2003.
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P. Kinget and N. Krishnapura, "Programmable Frequency Divider," US 6,281,721, Aug. 28, 2001.