Nagendra Krishnapura

Journal papers

A. K. Unnam, P. Banerjee and N. Krishnapura, "An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS," IEEE Solid-State Circuits Letters, doi: 10.1109/LSSC.2024.3412634.
A. Narayanan, A. Bhat and N. Krishnapura, "A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays," IEEE Journal of Solid-State Circuits, Accepted. (doi: 10.1109/JSSC.2024.3373620.)
P. Kumar and N. Krishnapura, "Signal-Strength Detector Based on CMOS-Inverter Supply Current," IEEE Solid-State Circuits Letters, vol. 6, pp. 237-240, 2023. doi: 10.1109/LSSC.2023.3307361.
R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, (doi: 10.1109/JSSC.2022.3171790.)
R. S. A. Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 186-195, Jan. 2022, (doi: 10.1109/TCSI.2021.3094679).
A. Bhat and N. Krishnapura, "A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 160-171, Jan. 2022. (doi: 10.1109/TCSI.2021.3096843).
Chithra, A. Narayanan, R. S. A. Kumar and N. Krishnapura, "Auto-zeroing Static Phase Offset in DLLs using a Digitally Programmable Sensing Circuit," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1788-1792, June 2021. (doi: 10.1109/TCSII.2021.3049134).
I. Mondal and N. Krishnapura, "Effects of AC Response Imperfections in True-Time-Delay Lines," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 4, pp. 1173-1177, April 2021. (doi: 10.1109/TCSII.2020.3027529).
R. S. Ashwin Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset," IEEE Transactions on Circuits and Systems I: Regular Papers. (doi: 10.1109/TCSI.2020.3013691).
Chithra and N. Krishnapura, "A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3693-3703, Nov. 2020. (doi: 10.1109/TCSI.2020.3013691).
M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 272-281, Feb. 2020. (doi: 10.1109/JSSC.2019.2945962).
N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3531-3543, Sept. 2019. (doi: 10.1109/TCSI.2019.2926143).
S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, "Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3393-3401, Sept. 2019. (doi: 10.1109/TCSI.2019.2926927).
R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3651-3661, Nov. 2018. (doi: 10.1109/TCSI.2018.2854707).
Abhishek Bhat and Nagendra Krishnapura, "On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 162-166, Feb. 2019. (doi: 10.1109/TCSII.2018.2842101).
I. Mondal and N. Krishnapura, "Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2703-2714, Sept. 2018. (doi: 10.1109/TCSI.2018.2799080).
Abhishek Bhat and Nagendra Krishnapura, "Low 1/f³ Phase Noise Quadrature LC VCOs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2127-2138, July 2018. (doi: 10.1109/TCSI.2017.2782247).
Imon Mondal and Nagendra Krishnapura, "A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 μm CMOS," IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2180-2193, Aug. 2017.(doi: 10.1109/JSSC.2017.2693229).
Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, "A 12.5 mW, 11.1 nV/rtHz, −115dB THD, < 1 µs Settling, 18 bit SAR ADC Driver in 0.6µm CMOS," IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 63, no. 5, pp. 443-447, May 2016. (doi: 10.1109/TCSII.2015.2504024).
Nagendra Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 61, no. 8, pp. 2219-2228, Aug. 2014. (doi: 10.1109/TCSI.2014.2333681)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay," IEEE Journal of Solid State Circuits, vol. 47, no. 8, pp. 1884-1895, August 2012. (doi: 10.1109/JSSC.2012.2196730)
Chembiyan Thambidurai and Nagendra Krishnapura, "On Pulse Position Modulation and its Application to PLLs for Spur Reduction," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 7, pp. 1483-1496, July 2011. (doi: 10.1109/TCSI.2011.2157749)
Nagendra Krishnapura, Abhishek Agrawal, and Sameer Singh, "A High IIP3 Third Order Elliptic Filter with Current Efficient Feedforward Compensated Opamps," IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 58, no. 4, pp. 205-209, April 2011. ( doi: 10.1109/TCSII.2011.2124571)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, "Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 676-680, Sep. 2010. (doi: 10.1109/TCSII.2010.2058496)
S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A Power Optimized Continuous-time ΔΣ ADC for Audio Applications," IEEE Journal of Solid State Circuits, vol. 43, no. 2, pp. 351-360, Feb. 2008. (doi: 10.1109/JSSC.2007.914263)
S. Pavan and N. Krishnapura, "Automatic Tuning of Time Constants in Continuous-Time Delta Sigma Modulators," IEEE Transactions on Circuits and Systems-II: Express Briefs, pp. 308-311, Apr. 2007.(doi: 10.1109/TCSII.2006.888920)
N. Krishnapura and Y. Tsividis, "Micropower low-voltage analog filter in a digital CMOS process," IEEE Journal of Solid State Circuits, vol. 38, no. 6, pp. 1063-1067, Jun. 2003. (doi: 10.1109/JSSC.2003.811986)
Y. Tsividis, N. Krishnapura, Y. Palaskas, L. Toth, "Internally varying analog circuits minimize power dissipation" IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 63-72, Jan. 2003. (doi: 10.1109/MCD.2003.1175109)
N. Krishnapura and Y. Tsividis, "Noise and Power Reduction in Filters Through the Use of Adjustable Biasing," IEEE Journal of Solid State Circuits, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. (doi: 10.1109/4.972141)
D. Frey, Y. Tsividis, G. Efthivoulidis, and N. Krishnapura, "Syllabic-companding Log Domain Filters," IEEE Transactions on Circuits and Systems II, vol 48, no. 4, pp. 329-339, Apr. 2001.(doi: 10.1109/82.933791)
N. Krishnapura, Y. Tsividis, and D. R. Frey, "Simplified Technique for Syllabic Companding in Log-domain Filters," Electronics Letters, vol. 36, no. 15, pp. 1257-1259, 20th Jul. 2000.(paper)
N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS," IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (doi: 10.1109/4.848211)
L. Toth, Y. Tsividis, and N. Krishnapura, "On the Analysis of Noise and Interference in Instantaneously Companding Signal Processors," IEEE Transactions on Circuits and systems-II, vol. 45, no. 9, pp. 1242-1249, Sep. 1998. (doi: 10.1109/82.718591)

Conference papers

Nagendra Krishnapura, "Analysis of Signal Transmission through Time-Varying Inductively Coupled Links," 2024 International Symposium on Circuits and Systems(ISCAS), Singapore, May 2024.
A. Narayanan and N. Krishnapura, "Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs," 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, 2023, pp. 1-5.
Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, and Nagendra Krishnapura, "A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India. (Co-recipient of the best paper award).
Sumit Kumar and Nagendra Krishnapura, "Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India.
Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura, "Bandpass filter and oscillator ICs with THD < -140dBc at 10Vppd for testing high-resolution ADCs," 2023 International Solid-State Circuits Conference, San Francisco, USA, Feb. 2023. doi: 10.1109/ISSCC42615.2023.10067771.
Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, and Nagendra Krishnapura, "A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process," 2020 International Symposium on Circuits and Systems(ISCAS), Seville, Spain, May 2020.
Vipul Bajaj, Anand Kannan, Minkle Paul, and Nagendra Krishnapura, "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters," 2020 International Symposium on Circuits and Systems(ISCAS), Seville, Spain, May 2020.
P. Bhattaru and N. Krishnapura, "A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems," 33rd International Conference on VLSI Design, Bangalore, India, 2020.
R. S. Ashwin Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset," The International Symposium on Integrated Circuits and Systems(ISICAS), Aug. 2020.
Ashwin Kumar R. S. and Nagendra Krishnapura, "A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter," 45th European Solid-State Circuits Conference, Krakow, Poland, Sep. 2019.
N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," The International Symposium on Integrated Circuits and Systems(ISICAS), Venice, Italy, Aug. 2019.
S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, "Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs," The International Symposium on Integrated Circuits and Systems(ISICAS), Venice, Italy, Aug. 2019.
Chithra and Nagendra Krishnapura, "Static Phase Offset Reduction Technique for Delay Locked Loops," 2019 International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan. doi: 10.1109/ISCAS.2019.8702613.
Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design," 2019 IEEE International Conference on Modeling of Systems, Circuits, and Devices (MOS-AK India 2019), Hyderabad, Feb. 2019.
Abhishek Bhat and Nagendra Krishnapura, "A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios," 2019 International Solid-State Circuits Conference, San Francisco, Feb. 2019.
R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," The International Symposium on Integrated Circuits and Systems(ISICAS), Taormina, Italy, Sep. 2018.
Imon Mondal and Nagendra Krishnapura, "Linearity- and Gain- Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load," Proc. 2018 International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence, Italy.
Praveen M V, Nagendra Krishnapura, "An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters," Proc. 2018 International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence, Italy.
Abhishek Bhat and Nagendra Krishnapura, "Low 1/f³ Phase Noise Quadrature LC VCOs," Proc. 2018 International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence, Italy.
Sumit Kumar and Nagendra Krishnapura, "Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM," Proc. 2017 IEEE ISCAS, Baltimore, USA, May 2017.
Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, "A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS," 2017 International Solid-State Circuits Conference, San Francisco, USA, Feb. 2017.
R. S. Ashwin Kumar and Nagendra Krishnapura, "A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset," 30th International Conference on VLSI Design, Hyderabad, India, Jan. 2017.
Abhishek Bhat and Nagendra Krishnapura, "A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs," Proc. 2016 International Symposium on Circuits and Systems (ISCAS), pp. 2070-2073, 22-25 May 2016, Montreal, Canada.
Imon Mondal and Nagendra Krishnapura, "Gain Enhanced High Frequency OTA with on-Chip Tuned Negative Conductance Load," 2015 International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, pp. 2085-2088, 20-23 May 2012. (paper)
Rakshitdatta K. S. and Nagendra Krishnapura, "On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback," 28th International Conference on VLSI Design, Bangalore, India, Jan. 2015.
Imon Mondal and Nagendra Krishnapura, "Accurate Constant Transconductance Generation Without Off-chip Components," 28th International Conference on VLSI Design, Bangalore, India, Jan. 2015.
Debasish Behera and Nagendra Krishnapura, "A 2-Channel 1MHz BW, 80.5dB DR ADC UsingΔΣ Modulator and Zero-ISI Filter," Proceedings of the 40th European Solid-State Circuits Conference, Venice, Italy, Sep. 2014.
A. Sukumaran, K. Karanjkar, S. Jhanwar, N. Krishnapura and S. Pavan, "1.2 V 285 µA Analog Front End Chip for a Digital Hearing Aid in 0.13µm CMOS," Proceedings of the 2013 Asian Solid State Circuits Conference, Singapore, Nov. 2013. (paper)
C. Preetham, G. Ramakrishnan, S. Kumar, A. Tamse, and N. Krishnapura, "Hand Talk-Implementation of a Gesture Recognizing Glove," 2013 Texas Instruments India Educators Conference, 2013, pp. 328-331. (paper)
Nagendra Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," Proceedings of the 2013 IEEE Custom Integrated Circuits Conference, September 2013. (paper)
Nagendra Krishnapura, "Introducing Negative Feedback with an Integrator as the Central Element," 2012 International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012. (paper, slides)
Nagendra Krishnapura, "Synthesis Based Introduction to Opamps and Phase Locked Loops," 2012 International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012. (paper, slides)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, September 2011. (paper, slides)
Nagendra Krishnapura, "Electronic Time Stretching for Fast Digitization," 2011 International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15-18 May 2011. (paper)
Nagendra Krishnapura, "Efficient Determination of Feedback DAC Errors for Digital Correction in Delta-Sigma A/D Converters," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
Shankar Parameswaran and Nagendra Krishnapura, "A 100µW Decimator for a 16 Bit 24kHz Bandwidth Audio ΔΣ Modulator," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
Chembiyan Thambidurai and Nagendra Krishnapura, "Spur Reduction in Wideband PLLs by Random Positioning of Charge Pump Pulses," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (paper, slides)
Nagendra Krishnapura, Varun Gupta, Neetin Agrawal, "Compact Lowpass Ladder Filters Using Tapped Coils," 2009 International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009. (paper, slides)
Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura, "A Comparison of Approaches to Carrier Generation in Zigbee Transceivers," 22nd International Conference on VLSI Design, New Delhi, India, 5-9 Jan 2009.(paper, slides)
S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A 90 microwatt 15 bit continuous-time delta-sigma ADC for digital audio," 33rd European Solid State Circuits conference, pp. 198-201, Sep. 2007, Munich, Germany. (paper)
N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission," IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)
N. Krishnapura and Y. Tsividis, "A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25um CMOS Process," 2001 VLSI Symposium on Circuits , pp. 179-182, Jun. 16 2001, Kyoto, Japan.(paper, slides)
N. Krishnapura and Y. Tsividis, "Dynamically Biased 1MHz Low-pass Filter with 61dB peak SNR and 112dB Input Range," IEEE International Solid State Circuits Conference, pp. 360-361,465, slide supplement pp. 292-293,507, Feb. 4-7 2001, San Fransisco, USA.(paper, slides)
N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS," European Solid State Circuits Conference, pp. 144-147, Sep 21-23 1999, Duisburg, Germany. (paper, slides)
N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)
N. Krishnapura, Y. Tsividis, K. Nagaraj, and K. Suyama, "Switched Capacitor Companding Filters," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California. (paper, slides)
L. Toth, Y. Tsividis, and N. Krishnapura, "Analysis of Noise and Interference in Companding Signal Processors," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, Jun 1-3 1998, Monterey, California. (paper, slides)

Tutorials at conferences

R. S. Ashwin Kumar and Nagendra Krishnapura, "Multi-channel Delta-Sigma Analog-to-Digital Converters Without Reset," 2023 IEEE Asia Pacific Conference On Circuits And Systems(APCCAS), 19-22 November 2023, Hyderabad, India.
Shanthi Pavan and Nagendra Krishnapura, "Linear Periodically Time-Varying Systems: Analysis and Applications," IEEE International Symposium on Circuits and Systems, 21-25 May 2023, Monterey, California, USA.
Saurabh Saxena and Nagendra Krishnapura, "Architecture and circuits for fractional-N clock synthesis in wireline/wireless applications," Full Day Tutorial at the 32nd International Conference on VLSI Design, 5-9 January 2019, New Delhi, India.
Saurabh Saxena and Nagendra Krishnapura, "High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery," Full Day Tutorial at the 31st International Conference on VLSI Design, 6-10 January 2018, Pune, India.
Shanthi Pavan and Nagendra Krishnapura, "Demystifying Time-Varying Systems," Half Day Tutorial at the 27th International Conference on VLSI Design, 4-8 January 2016, Kolkata, India.
N. Krishnapura, "Pedagogy of Negative Feedback Circuits," Half Day Tutorial at the 27th International Conference on VLSI Design, 5-9 January 2014, Mumbai, India. (abstract)
N. Krishnapura and S. Pavan, "Negative Feedback System and Circuit Design," Full Day Tutorial at the 22nd International Conference on VLSI Design, 5-9 January 2009, New Delhi, India. (abstract, Lecture and notes)
N. Krishnapura and S. Pavan, "Oversampling Analog to Digital Converters," Full Day Tutorial at the 21st International Conference on VLSI Design, 4-8 January 2008, Hyderabad, India. (abstract, Lecture and notes)

Patents

Nagendra Krishnapura and Pranav Kumar, "A signal strength indicator circuit," Indian patent 545473, 22 July 2024.
Chithra and Nagendra Krishnapura, "DLL and method for auto-zeroing static phase offset," Indian Patent 501606, 22 January 2024.
Ashwin Kumar R. S. and Nagendra Krishnapura, "Multi-channel ADC realization using a delta-sigma modulator without reset and a modulated-sinc-sum filter," Indian Patent 487682, 22 December 2023.
Abhishek Bhat and Nagendra Krishnapura, "Phase error measurement circuit with referenceless gain and offset calibration," Indian Patent 487682, 22 December 2023.
Madhukar Vallabhaneni and Nagendra Krishnapura, "A method of producing a linear current signal in a baseband Voltage-to-Current(V-I) converter," Indian Patent 481665, 13 December 2023.
Nagendra Krishnapura and Rakshitdatta K. S., "Method for determining distortion contribution of individual elements of a circuit," Indian Patent 375099, Aug. 23, 2021.
I. Shpantzer, M. Tseytlin, Y. Achiam, A. Salamon, I. Smilanski, O. Ritterbush, P. S. Cho, L. Guoliang, J. Khurgin, Y. Meiman, A. Demir, P. Feldmann, P. Kinget, N. Krishnapura, J. Roychowdhury, J. Schwarzwalder, C. Sciabarra, "System and method for code division multiplexed optical communication," US 7,167,651, Jan. 23, 2007.
I. Shpantzer, Y. Meiman, M. Tseytlin, O. Ritterbush, A. Salamon, P. Feldmann, A. Demir, P. Kinget, N. Krishnapura, J. Roychowdhury, "System and method for orthogonal frequency division multiplexed optical communication," US 7,076,169, Jul. 11, 2006.
N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,816,003, Nov. 9, 2004.
N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,717,461, Apr. 6, 2004.
N. Krishnapura and Y. Tsividis, "Circuits with Dynamic Biasing," US 6,683,492, Jan. 27, 2004.
P. Kinget and N. Krishnapura, "Glitch Free Phase Switching Synthesizer," US 6,671,341, Dec. 30, 2003.
P. Kinget and N. Krishnapura, "Programmable Frequency Divider," US 6,281,721, Aug. 28, 2001.

Nagendra Krishnapura

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