1. S.Pavan and G.Temes, ``Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks" IEEE Transactions on Circuits and Systems: Regular Papers , to appear in 2023.


2. S.Pavan, S.Manivannan and N.Basavaraj, ``Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining" IEEE Journal of Solid State Circuits , to appear in 2023.


3. R.Theertham, S.Ganta and S.Pavan, ``Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs" IEEE Journal of Solid State Circuits , November 2022.


4. N.Basavaraj, S.Manivannan and S.Pavan, ``Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter" IEEE Transactions on Circuits and Systems: Express Briefs , May 2022.


5. S.Manivannan and S.Pavan, ``Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property" IEEE Transactions on Circuits and Systems: Regular Papers , August 2022.


6. S.Pavan, ``Systematic Development of CMOS Fixed-Transconductance Bias Circuits" IEEE Transactions on Circuits and Systems: Express Briefs , May 2022.


7. S.Pavan and S.Manivannan, ``Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs" IEEE Transactions on Circuits and Systems: Regular Papers , February 2022.


8. R.Theertham and S.Pavan, ``Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback" IEEE Transactions on Circuits and Systems: Express Briefs , March 2022.


9. S.Pavan, T. Halder and A.Kannan, ``Continuous-time Incremental Delta-Sigma Modulators with FIR Feedback" IEEE Transactions on Circuits and Systems: Regular Papers , August 2021.


10. S.Manivannan and S.Pavan, ``A 65nm CMOS Continuous-Time Pipeline ADC achieving 70dB SNDR in 100MHz Bandwidth" IEEE Solid-State Circuits Letters , May 2021.


11. A.Baluni and S.Pavan, ``Analysis and Design of a 20 MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback " IEEE Journal of Solid-State Circuits , March 2021.


12. S.Pavan and H.Shibata, ``Continuous-time Pipelined Analog-to-Digital Converters: A Mini-Tutorial" IEEE Transactions on Circuits and Systems: Express Briefs , March 2021.


13. S.Manivannan and S.Pavan, ``Improved Continuous-Time Delta-Sigma Modulators with Embedded Active Filtering" IEEE Transactions on Circuits and Systems: Regular Papers , October 2020.


14. S.Billa, S.Dixit and S.Pavan, ``Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator" IEEE Journal of Solid State Circuits , October 2020.


15. R.Theertham, P.Koottala, S.Billa and S.Pavan, ``Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density " IEEE Journal of Solid State Circuits , September 2020.


16. S.Javvaji, V.Singhal, V.Menezes, R.Chauhan and S.Pavan, ``Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting " IEEE Journal of Solid State Circuits , September 2019.


17. R.Theertham and S.Pavan, ``Improved Offline Calibration of DAC Mismatch Errors in Delta Sigma Data Converters ," IEEE Transactions on Circuits and Systems: Express Briefs, October 2019.


18. R.Theertham and S.Pavan, ``Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators ," IEEE Transactions on Circuits and Systems: Regular Papers, August 2019.


19. K.Datta and S.Pavan, ``Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters ," IEEE Transactions on Circuits and Systems: Regular Papers, August 2019.


20. S.Pavan, ``An Alternative Approach to Bode's Noise Theorem ," IEEE Transactions on Circuits and Systems: Express Briefs, May 2019.


21. S. Manivannan and S.Pavan, ``Degradation of Alias Rejection in Continuous-Time Delta Sigma Modulators by Weak Loop-Filter Nonlinearities ," IEEE Transactions on Circuits and Systems: Regular Papers, October 2018.


22. S.Pavan and E.Klumperink, ``Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network," IEEE Transactions on Circuits and Systems: Regular Papers, October 2018.


23. S.Pavan, ``Improved Chopping in Continuous-time Delta-Sigma Modulators using FIR Feedback and N-path Techniques," IEEE Transactions on Circuits and Systems: Express Briefs, May 2018.


24. S.Pavan and E.Klumperink, ``Analysis of the Effect of Source Capacitance and Inductance on N-Path Mixers and Filters," IEEE Transactions on Circuits and Systems: Regular Papers, May 2018.


25. A.Jain and S.Pavan, ``Continuous-time Delta-Sigma Modulators using Time-Interleaved FIR Feedback," IEEE Transactions on Circuits and Systems: Regular Papers, February 2018.


26. H.Shibata, V.Kozlov, Z.Ji, A.Ganesan, H.Zhu, D. Paterson, J.Zhao, S.Patil and S.Pavan,``A 9 GS/s 1.125 GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164 dBFS/Hz NSD," IEEE Journal of Solid-State Circuits, December 2017.


27. S.Billa, A.Sukumaran and S.Pavan,``Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping," IEEE Journal of Solid-State Circuits, September 2017.


28. S.Pavan and E.Klumperink, ``Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network," IEEE Transactions on Circuits and Systems: Regular Papers, to appear, 2017.


29. N.Sinha, M.Rachid, S.Pavan and S.Pamarti ``Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components," IEEE Journal of Solid State Circuits, August 2017.


30. S.Pavan, ``Analysis of Chopped Integrators and its Application to Continuous-time Delta Sigma Modulator Design," IEEE Transactions on Circuits and Systems: Regular Papers, August 2017.


31. A.Sukumaran and S.Pavan, ``Continuous-time Delta Sigma Modulators with Dual Switched Capacitor Return-to-Zero DACs ," IEEE Journal of Solid State Circuits , July 2016.


32. J. de la Rosa, R.Schreier, K.P.Pun and S.Pavan, ``Next-generation Delta-Sigma Converters : Trends and Perspectives," IEEE Journal of Emerging Topics in Circuits and Systems , December 2015.


33. A.Sukumaran and S.Pavan, ``Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback," IEEE Journal of Solid State Circuits , November 2014.


34. R.S.Rajan and S.Pavan, ``Design Techniques for Continuous-Time Delta Sigma ADCs with Embedded Active Filtering" IEEE Journal of Solid State Circuits , October 2014.


35. S.Pavan and R.S.Rajan, ``Simplified Analysis and Simulation of the STF, NTF and Noise in CTDSMs," IEEE Transactions on Circuits and Systems: Express Briefs , Sept. 2014.


36. S.Pavan and R.S.Rajan, ``Interreciprocity in linear periodically time varying networks with sampled outputs," IEEE Transactions on Circuits and Systems: Express Briefs , Sept. 2014.


37. N.Rajesh and S.Pavan, `` Design of Lumped Component Programmable Delay Elements for Ultra-Wideband Beamforming," IEEE Journal of Solid State Circuits , August 2014.


38. S.Pavan, ``Continuous-time Delta Sigma Modulator Design using the Method of Moments," IEEE Transactions on Circuits and Systems: Regular Papers , June 2014.


39. A.Jain and S.Pavan, ``Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC," IEEE Transactions on Circuits and Systems: Regular Papers , May 2014.


40. T.Nandi, K.Boominathan and S.Pavan, ``Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC," IEEE Journal of Solid State Circuits , August 2013.


41. M.S.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan,``A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit," IEEE Sensors Journal , May 2013.


42. S.Pavan,``A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator," IEEE Transactions on Circuits and Systems : Express Briefs , February 2013.


43. P.Shettigar and S.Pavan,``Design Considerations for Wideband Single Bit Delta Sigma Modulators with FIR Feedback DACs IEEE Journal of Solid State Circuits , December 2012.


44. R.S.Rajan and S.Pavan,``Device Noise in Continuous Time Oversampled Converters," IEEE Transactions in Circuits and Systems, September 2012.


45. V.Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N. Nigania,``A 16 MHz BW 75 dB Dynamic Range CT Delta Sigma ADC Compensated for more than one Cycle Excess Loop Delay," IEEE Journal of Solid State Circuits, August 2012.


46. A. Jain, M. Venkatesan and S.Pavan,``Design and Analysis of a High Speed Continuous Time Delta Sigma Modulator using the Assisted Opamp Technique," IEEE Journal of Solid State Circuits, July 2012.


47. S. Thyagarajan, S. Pavan and P.Sankar,``Active filters using the Gm-assisted OTA-RC technique", IEEE Journal of Solid State Circuits, July 2011.


48. S. Pavan, ``On continuous-time Delta Sigma modulators with Return-to-Open DACs", IEEE Transactions on Circuits and Systems : Express Briefs, May 2011.


49. S. Pavan, ``Alias rejection of continuous-time oversampling converters with switched-capacitor feedback DACs", IEEE Transactions on Circuits and Systems : Regular Papers, February 2011.


50. V. Singh, N. Krishnapura and S. Pavan, ``Compensating for quantizer delay in excess of one clock cycle in continuous-time Delta-Sigma modulators", IEEE Transactions on Circuits and Systems : Express Briefs, September, 2010.


51. S. Pavan, ``Efficient simulation of weak nonlinearities in continuous-time oversampling converters", IEEE Transactions on Circuits and Systems : Regular Papers, August 2010. (paper)


52. S. Pavan and P. Sankar, "Power reduction in continuous-time Delta-Sigma modulators using the assisted opamp technique", IEEE Journal of Solid State Circuits, July 2010. (paper)


53. K. Reddy and S.Pavan, "A power efficient continuous time Sigma-Delta modulator with 15 MHz bandwidth and 70 dB dynamic range", Analog Integrated Circuits and Signal Processing, June 2010. (paper)


54. S. Pavan, "Systematic design centering of continuous-time oversampling converters", IEEE Transactions on Circuits and Systems : Express Briefs, March 2010 (paper)


55. T.Laxminidhi,V.Prasadu and S.Pavan, ``Widely Programmable High Frequency Active-RC Filters in CMOS Technology", IEEE Transactions on Circuits and Systems I : Regular Papers,(paper) February 2009.


56. S.Pavan, ``Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators", IEEE Transactions on Circuits and Systems II : Express Briefs, November 2008.(paper).


57. S. Pavan, ``Power and Area Efficient Adaptive Equalization at Microwave Frequencies", IEEE Transactions on Circuits and Systems I : Regular Papers, July 2008.(paper)


58. S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, ``A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications," IEEE Journal of Solid State Circuits, February 2008.(paper)


59. P. Sankar and S. Pavan,``Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators", IEEE Transactions on Circuits and Systems : Express Briefs, December 2007.(paper)


60. K. Reddy and S. Pavan, ``Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter", IEEE Transactions on Circuits and Systems : Regular Papers, October 2007.(paper)


61. S. Pavan and T. Laxminidhi, ``Accurate Characterization of Integrated Continuous Time Filters", IEEE Journal of Solid State Circuits, August 2007.(paper)


62. T. Laxminidhi and S. Pavan,``Efficient Design Centering of High Frequency Continuous Time Filters", IEEE Transactions on Circuits and Systems : Regular Papers, July 2007.(paper)


63. S. Pavan and N. Krishnapura, ``Automatic Tuning of Time-Constants in Continuous-Time Delta-Sigma Modulators", IEEE Transactions on Circuits and Systems : Express Briefs, April 2007.(paper)


64. S. Pavan and R. Tiruvuru, ``Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers" IEEE Transactions on Circuits and Systems : Regular Papers, February 2007. (paper)


65. V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar,`` A Distortion Compensating Flash Analog to Digital Conversion Technique," IEEE Journal of Solid State Circuits. September 2006. (paper)


66. S. Pavan and S. Shivappa,``Nonidealities in Traveling Wave and Transversal FIR Filters Operating at Microwave Frequencies", IEEE Transactions on Circuits and Systems : Regular Papers , January 2006. (paper)


67. S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau,`` Design considerations for Integrated Modulator Drivers in SiGe Technology", International Journal of High Speed Electronics and Systems, September 2005.


68. S. Pavan, ``Continuous-Time Integrated FIR Filters at Microwave Frequencies", IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing, January 2004. (paper)


69. K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, ``A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-um digital CMOS process", IEEE Journal of Solid State Circuits, December 2000.


70. S. Pavan and Y. Tsividis, ``Time Scaled Electrical Networks - Properties and Applications in the Design of Programmable Analog Filters", IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, , Vol. 47, No.2, pp. 161-5, February 2000.(paper)


71. S. Pavan, Y. Tsividis and K. Nagaraj, `` Widely Programmable High Frequency Continuous Time Filters in Digital CMOS Technology", IEEE Journal of Solid State Circuits,, Vol. 35, No.4, April 2000.(paper)


72. S. Pavan and Y. Tsividis, ``An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning'', IEEE Transactions on Circuits and Systems-I, vol. 45, no. 9, pp. 1242-1249, May 1998. (paper)

1. K.Singh and S.Pavan, ``A 14 bit dual channel incremental continuous-time Delta Sigma modulator for multiplexed data acquisition," IEEE International Conference on VLSI Design}, pages 1--5. IEEE, 2016.


2. S.Billa, A.Sukumaran, and S.Pavan, ``A 280uW, 24kHz BW, 98.5dB SNDR, chopped single-bit CTDSM achieving less than 10 Hz 1/f noise corner without chopping artifacts," IEEE International Solid State Circuits Conference (ISSCC), pages 1--2. IEEE, 2016.


3. A.Sukumaran and S.Pavan, ``A continuous-time Delta Sigma modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC," Proceedings of the European Solid-State Circuits Conference (ESSCIRC)}, pages 217--220. IEEE, 2015.


4. N.Rajesh and S.Pavan, ``Programmable analog pulse shaping for ultra-wideband applications," IEEE International Symposium on Circuits and Systems (ISCAS)}, pages 461--464. IEEE, 2015.


5. N.Rajesh and S.Pavan, ``Improved characterization of differential multi-GHz integrated amplifiers and filters," Proceedings of the IEEE International Microwave Symposium, pages 461--464. IEEE, 2015.


6. S.Krishnan and S.Pavan, ``A 10 Gbps eye opening monitor in 65nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS)}, pages 3028--3031. IEEE, 2015.


7. R.Rajan and S.Pavan, ``A 5mW CT Delta Sigma ADC with embedded second order active filter and VGA achieving 82dB dynamic range in 2MHz bandwidth," 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC)}, pages 156--158, 2014.


8. S.Pavan, `` Efficient estimation of the signal and noise transfer functions of a continuous time Delta Sigma modulator," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, pages 1--4, 2014.


9. M.Veeramani, N.Ratchagar, E.Bhattacharya, S.Pavan, S.Prakash, and A.Chadha, ``Compact silicon biosensor for the clinical range estimation of blood serum triglyceride,'' IEEE SENSORS , pages 1--4. IEEE, 2013.


10. A.Sukumaran and S.Pavan, ``A 280uW audio continuous-time Delta Sigma modulator with 103 dB DR and 102 dB A-Weighted SNR," Proceedings of the Asian Solid State Circuits Conference, Singapore , pages 1--4, 2013.


11. A.Sukumaran, K.Karanjkar, S.Jhanwar, N.Krishnapura, and S.Pavan, "A 1.2V 285uA analog front end chip for a digital hearing aid in 0.13um CMOS," Proceedings of the Asian Solid State Circuits Conference, Singapore , pages 1--4, 2013.


12. N.Rajesh and S.Pavan, "A lumped component programmable delay element for ultra-wideband beamforming," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose, California , pages 1--4, 2013.


13. A.Jain and S.Pavan, "Efficient characterization of continuous time oversampling converters using a duobinary test interface," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing pages 1--4, 2013.


14. P.Shettigar and S.Pavan, "A 15mW 3.6 GS/s CT-Delta Sigma ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS, " IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 156--158, 2012.


15. R.S. Rajan and S.Pavan, "Device noise in continuous-time $\Delta$$\Sigma$ modulators with Switched-Capacitor feedback DACs," 2012 IEEE International Symposium on Circuits and Systems (ISCAS) , pages 524--527, 2012.


16. T.Nandi, K.Boominathan, and S.Pavan, "A continuous-time Delta Sigma modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) , pages 1--4, 2012.


17. A. Jain, M. Venkateswaran and S. Pavan, "A 4mW 1GS/S continuous-time Delta Sigma modulator with 15.6 MHz bandwidth and 67 dB dynamic range ", Proceedings of the IEEE European Solid State Circuits Conference, Helsinki, Finland, September 2011.


18. V. Singh, N. Krishnapura, S. Pavan, B. Vigrah am, D. Behera and N. Nigania, "A 16MHz BW 75dB DR CT DS ADC Compensated for More Than One Cycle Excess Loop Delay ", Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, September 2011.


19. S. Pavan, "The inconvenient truth about alia s rejection in continuous-time oversampling converters", Proceedings of the IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Bra zil, May 2011.


20. S. Thyagarajan, S. Pavan and P.Sankar, "Low distortion active-filters using the Gm-assisted Active-RC technique", Proce edings of the European Solid State Circuits Conference, Seville, Spain, Se ptember 2010.


21. S. Pavan, "Understanding weak nonlinearities in continuous-time oversampling converters", IEEE International Symposium on Circuits and Systems (ISCAS), Paris, May 2010.


22. S.Pavan and P.Sankar, "A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range", European Solid State Circuits Conference (ESSCIRC), Athens, Greece, September 2009 (paper).


23. Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, "A Digitally Assisted Baseband Filter with 9 MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain", International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009.(paper)


24. S.Saxena,P.Sankar and S.Pavan, "Automatic Tuning of Time Constants in Single-bit Continuous-time Delta Sigma Modulators",International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009. (paper)


25. V.Hareesh, S.Pavan and E.Bhattacharya, "Readout Circuit Design for an EISCAP Biosensor", IEEE Biomedical Circuits and Systems Conference, November 2008.(paper)


26. K. Reddy and S.Pavan, "A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range", Proceedings of the European Solid State Circuits Conference, Edinburgh, September 2008.(paper)


27. S. Pavan, "Power and Area Efficient Analog Adaptive Equalization", IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, May 2008.(paper)


28. T. Laxminidhi, V. Prasadu and S. Pavan, "A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS", Proceedings of the Custom Integrated Circuits Conference, San Jose, September 2007.(paper)


29. S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, "A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio", Proceedings of the European Solid State Circuits Conference, Munich, September 2007.(paper)


30. T. Laxminidhi and S. Pavan, "Efficiently Design Centering High Frequency Integrated Continuous-time Filters", IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans(paper)


31. S. Pavan, "Singly Terminated Transmission Line Filters for High Speed Adaptive Equalization", IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans.(paper)


32. S. Pavan and T.Laxminidhi, " A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters," Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2006, San Jose, September 2006.(paper)


33. S. Pavan and T.Laxminidhi, " A 70-500 MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects," Proceedings of the IEEE European Solid State Circuits Conference, ESSCIRC 2006, Switzerland, September 2006. (paper)


34. S. Murali and S. Pavan," Rapid Simulation of Current Steering DACs using Verilog-A," Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2006, San Jose, September 2006.(paper)


35. A. Sharma and S. Pavan,"A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper)


36. K. Reddy and S. Pavan,"Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter ," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides)


37. T. Rajesh and S. Pavan, "Transmission Line based FIR Structures for High Speed Adaptive Equalization," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides)


38. S. Pavan and S. Shivappa," Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers", IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe , May 2005.(paper) (slides)


39. S. Pavan, " A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver , May 2004.(paper) (slides)


40. S. Pavan, " Analog FIR Filters at Microwave Frequencies ", Proceedings of the National Conference on Communications, IIT Madras, Chennai, February 2003.(paper)


41. G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, " A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ", Proceedings of the Custom Integrated Circuits Conference, May 2001. (paper)


42. K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode", International Solid State Circuits Conference, February 2000. (paper)


43. K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000.


44. S. Pavan, Y. Tsividis and K. Nagaraj, " A 60-350 MHz Programmable Analog Filter in a Digital CMOS Process", Proceedings of the European Solid State Circuits Conference,, September 21-23 1999, Duisburg, Germany.(paper, slides)


45. S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of Accumulation MOS Capacitors for Analog Design in Digital VLSI Processes", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, May 31-June 3 1999, Orlando, Florida.(paper, slides )


46. N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)


47. S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California.(paper)

Patents

1. Shanthi Pavan and Siva Thyagarajan, "Low distortion filters", US 9,000,389


2. Shanthi Pavan, "Power and Area Efficient Adaptive Equalization", US 7,471,751


3. Shanthi Pavan, "Distortion Compensation Technique for Flash Type Analog-to-Digital Converters", Europe 1,207,624


4. John Wang, Sudeep Bhoja and Shanthi Pavan, "Method and Apparatus for Improved High-speed Adaptive Equalization", US 7,301,997.


5. Shanthi Pavan, "Integrated circuit implementation for power and area efficient adaptive equalization", US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.


6. John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, "Method and apparatus for improved high-speed adaptive equalization", US 7,003,228, Feb. 21, 2006.


7. Shanthi Pavan et al.,"Mobility Compensation in MOS Integrated Circuits", US 6,822,505, 23 Nov. 2004.


8. Shanthi Pavan et al., "Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier", US 6,552,615, 22 Apr. 2003.


9. Shanthi Pavan et al., "Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells", US 6,545,567, 8 Apr. 2003.


10. Shanthi Pavan, "Fixed Transconductance Bias Apparatus", US 6,400,185, 4 Jun. 2002.


11. Shanthi Pavan et al., "Fast Acting Polarity Detector", US 6,369,726, 2 Apr. 2002.


12. Shanthi Pavan, "Low Distortion Sample-and-Hold Circuit", US 6,323,697, 27 Nov. 2001.


13. Shanthi Pavan, "High Frequency Boost Technique", US 6,304,134, 16 Oct. 2001


14. Shanthi Pavan et al., "Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation", US 5,945,889, 31 Aug. 1999.

1. S. Pavan, C. Srinivasan and P. Easwaran, ``System Level Aspects of A/D Converter Designs", half day tutorial at the International Conference on VLSI Design, Hyderabad, India, 2006.


2. S. Pavan and N. Krishnapura, ``Oversampled Data Converter Design", full day tutorial at the International Conference on VLSI Design, Hyderabad, India, 2008.


3. K. Balemarthy and S. Pavan, ``Signal Processing for Fiber Optic Communication", half day tutorial at the National Conference on Communication, Bombay, India, 2008.


4. N. Krishnapura and S. Pavan, ``Negative Feedback Circuit and System Design," full day tutorial at the International Conference on VLSI Design, New Delhi, India, 2009.


5. S. Pavan, ``Design Techniques for High-Performance Continuous-time Delta Sigma Conversion," half day tutorial at the European Solid State Circuits Conference, Seville, Spain, 2010.


6. S. Pavan, ``High-Performance Continuous-time Delta Sigma Converters," Educational Sessions of the Custom Integrated Circuits Conference, San Jose, USA, 2010.

Books

( Order it online from Springer )

( Order it online from Amazon.com )

Manuals

Solutions Manual : Operation and Modeling of the MOS Transistor (by Yannis Tsividis)
Mehran Bagheri & Shanthi Pavan

McGraw Hill Publishing Company, New York, NY