Conference Publications

  1. K.Singh and S.Pavan, ``A 14 bit dual channel incremental continuous-time Delta Sigma modulator for multiplexed data acquisition," IEEE International Conference on VLSI Design}, pages 1--5. IEEE, 2016.

  2. S.Billa, A.Sukumaran, and S.Pavan, ``A 280uW, 24kHz BW, 98.5dB SNDR, chopped single-bit CTDSM achieving less than 10 Hz 1/f noise corner without chopping artifacts," IEEE International Solid State Circuits Conference (ISSCC), pages 1--2. IEEE, 2016.

  3. A.Sukumaran and S.Pavan, ``A continuous-time Delta Sigma modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC," Proceedings of the European Solid-State Circuits Conference (ESSCIRC)}, pages 217--220. IEEE, 2015.

  4. N.Rajesh and S.Pavan, ``Programmable analog pulse shaping for ultra-wideband applications," IEEE International Symposium on Circuits and Systems (ISCAS)}, pages 461--464. IEEE, 2015.

  5. N.Rajesh and S.Pavan, ``Improved characterization of differential multi-GHz integrated amplifiers and filters," Proceedings of the IEEE International Microwave Symposium, pages 461--464. IEEE, 2015.

  6. S.Krishnan and S.Pavan, ``A 10 Gbps eye opening monitor in 65nm CMOS," IEEE International Symposium on Circuits and Systems (ISCAS)}, pages 3028--3031. IEEE, 2015.

  7. R.Rajan and S.Pavan, ``A 5mW CT Delta Sigma ADC with embedded second order active filter and VGA achieving 82dB dynamic range in 2MHz bandwidth," 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC)}, pages 156--158, 2014.

  8. S.Pavan, `` Efficient estimation of the signal and noise transfer functions of a continuous time Delta Sigma modulator," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, pages 1--4, 2014.

  9. M.Veeramani, N.Ratchagar, E.Bhattacharya, S.Pavan, S.Prakash, and A.Chadha, ``Compact silicon biosensor for the clinical range estimation of blood serum triglyceride,'' IEEE SENSORS , pages 1--4. IEEE, 2013.

  10. A.Sukumaran and S.Pavan, ``A 280uW audio continuous-time Delta Sigma modulator with 103 dB DR and 102 dB A-Weighted SNR," Proceedings of the Asian Solid State Circuits Conference, Singapore , pages 1--4, 2013.

  11. A.Sukumaran, K.Karanjkar, S.Jhanwar, N.Krishnapura, and S.Pavan, "A 1.2V 285uA analog front end chip for a digital hearing aid in 0.13um CMOS," Proceedings of the Asian Solid State Circuits Conference, Singapore , pages 1--4, 2013.

  12. N.Rajesh and S.Pavan, "A lumped component programmable delay element for ultra-wideband beamforming," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose, California , pages 1--4, 2013.

  13. A.Jain and S.Pavan, "Efficient characterization of continuous time oversampling converters using a duobinary test interface," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing pages 1--4, 2013.

  14. P.Shettigar and S.Pavan, "A 15mW 3.6 GS/s CT-Delta Sigma ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS, " IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 156--158, 2012.

  15. R.S. Rajan and S.Pavan, "Device noise in continuous-time $\Delta$$\Sigma$ modulators with Switched-Capacitor feedback DACs," 2012 IEEE International Symposium on Circuits and Systems (ISCAS) , pages 524--527, 2012.

  16. T.Nandi, K.Boominathan, and S.Pavan, "A continuous-time Delta Sigma modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) , pages 1--4, 2012.

  17. V.Singh, N.Krishnapura, S.Pavan, B.Vigraham, N.Nigania, and D.Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pages 1--4, 2011.

  18. S.Pavan, "The inconvenient truth about alias rejection in continuous time Delta Sigma converters," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)}, pages 526--529, 2011.

  19. A. Jain, M. Venkateswaran and S. Pavan, "A 4mW 1GS/S continuous-time Delta Sigma modulator with 15.6 MHz bandwidth and 67 dB dynamic range ", Proceedings of the IEEE European Solid State Circuits Conference, Helsinki, Finland, September 2011.

  20. V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera and N. Nigania, "A 16MHz BW 75dB DR CT DS ADC Compensated for More Than One Cycle Excess Loop Delay ", Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, September 2011.

  21. S. Pavan, "The inconvenient truth about alias rejection in continuous-time oversampling converters", Proceedings of the IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

  22. S. Thyagarajan, S. Pavan and P.Sankar, "Low distortion active-filters using the Gm-assisted Active-RC technique", Proceedings of the European Solid State Circuits Conference, Seville, Spain, September 2010.

  23. S. Pavan, "Understanding weak nonlinearities in continuous-time oversampling converters", IEEE International Symposium on Circuits and Systems (ISCAS), Paris, May 2010.

  24. S.Pavan and P.Sankar, "A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range", European Solid State Circuits Conference (ESSCIRC), Athens, Greece, September 2009 (paper).

  25. Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, "A Digitally Assisted Baseband Filter with 9 MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain", International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009.(paper)

  26. S.Saxena,P.Sankar and S.Pavan, "Automatic Tuning of Time Constants in Single-bit Continuous-time Delta Sigma Modulators",International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009. (paper)

  27. V.Hareesh, S.Pavan and E.Bhattacharya, "Readout Circuit Design for an EISCAP Biosensor", IEEE Biomedical Circuits and Systems Conference, November 2008.(paper)

  28. K. Reddy and S.Pavan, "A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range", Proceedings of the European Solid State Circuits Conference, Edinburgh, September 2008.(paper)

  29. S. Pavan, "Power and Area Efficient Analog Adaptive Equalization", IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, May 2008.(paper)

  30. T. Laxminidhi, V. Prasadu and S. Pavan, "A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS", Proceedings of the Custom Integrated Circuits Conference, San Jose, September 2007.(paper)

  31. S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, "A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio", Proceedings of the European Solid State Circuits Conference, Munich, September 2007.(paper)

  32. T. Laxminidhi and S. Pavan, "Efficiently Design Centering High Frequency Integrated Continuous-time Filters", IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans(paper)

  33. S. Pavan, "Singly Terminated Transmission Line Filters for High Speed Adaptive Equalization", IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans.(paper)

  34. S. Pavan and T.Laxminidhi, " A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters," Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2006, San Jose, September 2006.(paper)

  35. S. Pavan and T.Laxminidhi, " A 70-500 MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects," Proceedings of the IEEE European Solid State Circuits Conference, ESSCIRC 2006, Switzerland, September 2006. (paper)

  36. S. Murali and S. Pavan," Rapid Simulation of Current Steering DACs using Verilog-A," Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2006, San Jose, September 2006.(paper)

  37. A. Sharma and S. Pavan,"A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper)

  38. K. Reddy and S. Pavan,"Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter ," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides)

  39. T. Rajesh and S. Pavan, "Transmission Line based FIR Structures for High Speed Adaptive Equalization," IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides)

  40. S. Pavan and S. Shivappa," Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers", IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe , May 2005.(paper) (slides)

  41. S. Pavan, " A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits", IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver , May 2004.(paper) (slides)

  42. S. Pavan, " Analog FIR Filters at Microwave Frequencies ", Proceedings of the National Conference on Communications, IIT Madras, Chennai, February 2003.(paper)

  43. G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, " A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ", Proceedings of the Custom Integrated Circuits Conference, May 2001. (paper)

  44. K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode", International Solid State Circuits Conference, February 2000. (paper)

  45. K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000.

  46. S. Pavan, Y. Tsividis and K. Nagaraj, " A 60-350 MHz Programmable Analog Filter in a Digital CMOS Process", Proceedings of the European Solid State Circuits Conference,, September 21-23 1999, Duisburg, Germany.(paper, slides)

  47. S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of Accumulation MOS Capacitors for Analog Design in Digital VLSI Processes", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, May 31-June 3 1999, Orlando, Florida.(paper, slides )

  48. N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)

  49. S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California.(paper)

Patents

  1. Shanthi Pavan, "Integrated circuit implementation for power and area efficient adaptive equalization", US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.

  2. John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, "Method and apparatus for improved high-speed adaptive equalization", US 7,003,228, Feb. 21, 2006.

  3. Shanthi Pavan et al.,"Mobility Compensation in MOS Integrated Circuits", US 6,822,505, 23 Nov. 2004.

  4. Shanthi Pavan et al., "Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier", US 6,552,615, 22 Apr. 2003.

  5. Shanthi Pavan et al., "Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells", US 6,545,567, 8 Apr. 2003.

  6. Shanthi Pavan, "Fixed Transconductance Bias Apparatus", US 6,400,185, 4 Jun. 2002.

  7. Shanthi Pavan et al., "Fast Acting Polarity Detector", US 6,369,726, 2 Apr. 2002.

  8. Shanthi Pavan, "Low Distortion Sample-and-Hold Circuit", US 6,323,697, 27 Nov. 2001.

  9. Shanthi Pavan, "High Frequency Boost Technique", US 6,304,134, 16 Oct. 2001

  10. Shanthi Pavan et al., "Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation", US 5,945,889, 31 Aug. 1999.