VLSI Broadband Communication Circuits, Aug-Dec 2007: References
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Handouts
References
Digital transmission, clock and data recovery
- William J. Dally, John W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
- IEEE Journal of Solid State Circuits, IEEE. http://ieeexplore.ieee.org
- Behzad Razavi, Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design, IEEE Press, 1996.
- Behzad Razavi, Phase Locking in High Performance Systems-From Devices to Architectures, IEEE Press, 2003.
- Behzad Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2002.
Analog circuit design
- Analog Integrated Circuit Design, David Johns and Ken Martin, John Wiley & Sons, 1997.
- Mixed Analog Digital VLSI Devices and Technology (An introduction), Y. Tsividis, World Scientific, New Jersey, 2002.
- Analysis and design of Analog Integrated Circuits, Gray, Hurst, Lewis, and Meyer, 4th Edition, John Wiley and Sons.
- Design of Analog Integrated Circuits and Systems, K. R. Laker and W.M.C. Sansen, McGraw-Hill, January 1994
- "Design of Analog CMOS Integrated Circuits", Behzad Razavi, McGraw-Hill,August 2000.
- EE539, Analog IC design pages: 2007, 2006.
Suggested topics for presentation
Circuit techniques
- Multi-gigabit-per-second silicon bipolar ICs for future
optical-fiber transmission systems; Rein, H.-M.;
Solid-State Circuits, IEEE Journal of Volume 23, Issue
3, June 1988 Page(s):664 - 675
- Injection locked frequency dividers
- A family of low-power truly modular programmable
dividers in standard 0.35-?m CMOS technology Vaucher,
C.S.; Ferencic, I.; Locher, M.; Sedvallson, S.;
Voegeli, U.; Wang, Z.; Solid-State Circuits, IEEE
Journal of Volume 35, Issue 7, July 2000 Page(s):1039 -
1045
- Broadband ESD protection circuits in CMOS technology
Galal, S.; Razavi, B.; Solid-State Circuits, IEEE
Journal of Volume 38, Issue 12, Dec 2003 Page(s):2334 -
2340
- A CMOS 10-gb/s power-efficient 4-PAM transmitter
Farzan, K.; Johns, D.A.; Solid-State Circuits, IEEE
Journal of Volume 39, Issue 3, March 2004 Page(s):529 -
532
- A 125-MHz CMOS mixed-signal equalizer for gigabit
ethernet on copper wire Frequency 1 - size 14162 bytes
--- Tai-Cheng Lee, Behzad Razavi. 2001 IEEE Custom
Integrated Circuits Conference, Vol. 14, pp. 75 - 75,
May 2001.
- A 4-tap 125-MHz mixed-signal echo canceller for gigabit
ethernet on copper wire Frequency 1 - size 13262 bytes
--- Tai-Cheng Lee, Behzad Razavi. 2000 IEEE Custom
Integrated Circuits Conference, Vol. 13, pp. 461 - 464,
May 2000.
- A 125-MHz mixed-signal echo canceller for gigabit
Ethernet on Copper wire Frequency 1 - size 27472 bytes
--- Tai-Cheng Lee, Behzad Razavi. IEEE Journal of
Solid-State Circuits, Vol. 36, pp. 366 - 373, Mar 2001.
Clock and data recovery
- A 155-MHz clock recovery delay- and phase-locked loop
Lee, T.H.; Bulzacchelli, J.F.; Solid-State Circuits,
IEEE Journal of Volume 27, Issue 12, Dec. 1992
Page(s):1736 - 1746
- Clock recovery circuits with instantaneous locking
Banu, M.; Dunlop, A.E.; Electronics Letters Volume 28,
Issue 23, 5 Nov. 1992 Page(s):2127 - 2130
- A 100-MHz, 50-\Omega, --45-dB distortion, 3.3-V CMOS
line driver for ethernet and fast ethernet networking
applications Frequency 2 - size 19825 bytes --- Joseph
N. Babanezhad. IEEE Journal of Solid-State Circuits,
Vol. 34, pp. 1044 - 1050, August 1999.
- Analog timing recovery for a noise-predictive
decision-feedback equalizer Frequency 1 - size 19333
bytes --- John P. Keane, Michael Q. Le, Paul
J. Hurst. IEEE Journal of Solid-State Circuits,
Vol. 38, pp. 338 - 342, Feb 2003.
- A CMOS analog timing recovery circuit for PRML
detectors Frequency 1 - size 34994 bytes --- Pierte
Roo, Richard R. Spencer, Paul J. Hurst. IEEE Journal of
Solid-State Circuits, Vol. 35, pp. 56 - 65, January
2000.
Equalization
- Kasturia, S. and Winters, J.H., "Techniques for
high-speed implementation of nonlinear cancellation",
IEEE Journal on Selected Areas in
Communications, Volume 9, Issue 5, June 1991
Page(s):711 - 717
- S. Pavan, " Continuous-Time Integrated FIR Filters at
Microwave Frequencies", IEEE Transactions on Circuits
and Systems-II, Analog and Digital Signal Processing,
January 2004.
Complete tranceivers
- Bulzacchelli, J. F. et al., A 10-Gb/s 5-Tap DFE/4-Tap
FFE Transceiver in 90-nm CMOS Technology, IEEE Journal
of Solid State Circuits, pp 2885-2900, vol. 41, no. 12,
Dec. 2006.
- R. Payne et al., "A 6.25-Gb/s Binary Transceiver in
0.13-?m CMOS for Serial Data Transmission Across High
Loss Legacy Backplane Channels", IEEE Journal of Solid
State Circuits, pp 2646-2657, vol. 40, no. 12,
Dec. 2005.
- A 10-Gb/s two-dimensional eye-opening monitor in
0.13-/spl mu/m standard CMOS Analui, B.; Rylyakov, A.;
Rylov, S.; Meghelli, M.; Hajimiri, A.; Solid-State
Circuits, IEEE Journal of Volume 40, Issue 12,
Dec. 2005 Page(s):2689 - 2699
- A CMOS transceiver analog front-end for gigabit
ethernet over CAT-5 cables Frequency 1 - size 11161
bytes --- Pierte Roo, Sehat Sutardja, Shuran Wei,
Farbod Aram, Yi Cheng. IEEE International Solid-State
Circuits Conference, Vol. 44, pp. 310 - 311, Feb 2001.
- A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet
Frequency 1 - size 30719 bytes --- James Everitt, James
F. Parker, Paul Hurst, Dave Nack, Kishan Rao
Konda. IEEE Journal of Solid-State Circuits, Vol. 33,
pp. 2169 - 2177, December 1998.