Completed students

• Nikhil K.S (Ph.D)
UG Course : B.Tech (Electronics and Communications Engineering)
College : Mohandas College of Engineering and Technology, Anad, Thiruvananthapuram.
Year of Graduation :     2010
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PG Course : M.E (VLSI Design)
College : College of Engineering Guindy, Chennai-600025
Year of Graduation :     2012
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Date of Joining in IIT Madras : 16th July 2012
Research Area :    "Modeling of LDMOS Transistors"
Brief description of work:    "Analysis and compact modeling of LDMOS  (Lateral Double Diffused Metal Oxide -
Semiconductor) transistors including the snapback voltage model."
Publications:

1.  S. Gupta, K. S. Nikhil, A. Chakravorty, A. DasGupta, and N. DasGupta, “Prediction of IMD behaviour in LDMOS Transistor Amplifiers using a Physics-based Large Signal Compact Model,” in International Confer- ence on Emerging Electronics (ICEE 2016). IEEE, accepted.
2. K. S. Nikhil, N. DasGupta, A. DasGupta and A. Chakravorty,"Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors" Trans Electron Devices, vol.63, No.10, pp. 4003-4010, October 2016.
3. N. Prasad, P. Sarangapani, K. S. Nikhil, N. DasGupta, A. DasGupta and A. Chakravorty, "An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors", Trans Electron Devices, vol.62, No.3 pp. 919-926, March 2015.
• Shon Yadav (Ph.D)
UG Course :  B.E (Electronics and Communications Engineering)
College :  Walchand College of Engineering, Sangli, Maharashtra.
Year of Graduation :     2009
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Date of Joining in IIT Madras :    21st December 2011
Research area :  "Compact modeling of Silicon Germanium Hetero junction Bipolar Transistor (SiGe HBT)"
Brief Description of Work :  "Compact modeling of the lateral non-quai-static effect in base impedance in Si-Ge Heterojunction bipolar transistors."
Pulications:

1.  S. Yadav, A. Chakravorty, "Compact Modeling of the Lateral Non-Quasi- Static Effect in SiGe HBTs" , VLSI Design conference, January 2017.
2.  S.Yadav, A.Chakravorty, and M.Schroter, "Modeling of the lateral emitter current crowding effect in SiGe HBTs", IEEE Transaction on Electron Devices, Vol.63, no.11,2016.
3.   S. Yadav, A. Chakravorty, and M. Schroter, "Hybrid small-signal π-model for the lateral NQS effect in SiGe HBTs", Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 154157, 2016.
4.  S. Yadav, A. Chakravorty, "Hybrid two-section model for the small-signal current crowding effect in SiGe HBTs", International Confer- ence on Emerging Electronics (ICEE), 2016.
5.  S. Yadav, A. Chakravorty, "Analysis and implementation of the π- and ex- tended π-EC models for lateral NQS effect in SiGe HBTs", International Workshop on Physics of Semiconductor Devices (IWPSD), 2015.
6.  S.Yadav, A.Chakravorty, and M.Schroter, "Small-signal modeling of the lateral NQS effect in SiGe HBTs", Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp.203206, 2014.
• Sathyasree (Ph.D)
UG Course :  B.E (Electronics and Communications Engineering)
College :   PTR College of Engineering, Madurai
Year of Graduation :     2005
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PG Course :   M.E
College :   Thiagarajar College of Engineering, Madurai
Year of Graduation :    2017
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Date of Joining in IIT Madras :    13th July 2013
Research Area : "Microelectronics"
Brief description of work: "Compact Modelling of On-Chip Spiral Inductors "
Publications :
1.  Sathyasree J, Venkata narayana Vanukuru, Deleep R Nair and Anjan Chakravorty, "Modeling of Rectangular On-Chip Spiral Inductors", 2016 Asia-Pacific Microwave Conference.
• Shubham Gupta (MS)
UG Course : B.Tech (Electronics and Communication Engineering )
University : National Institute of Technology (NIT) Silchar, Assam.
Year of Graduation :     2014

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Date of joining in IIT Madras : 14th July 2014
Research Area : " Microelectronics and VLSI "
Brief description of work : "A Comprehensive analysis of Intermodulation distortion (IMD) behaviour in silicon - on - insulator lateral double-diffused metal-oxide-semiconductor (SOI-LDMOS) transistor amplifiers is carried out using a physics -based large signal compact model". The non-linear mechanisms inside the transistor which cause such sweet spots (Intermodulation Distortion Minima) to occur is understood from simple memoryless IMD model. These sweet spots depend on device parameters, bias and input power. At device level, one can improve the (SOI-LDMOS) technology by studying how device parameters affect IMD.At circuit level, the dependency of sweet spots with gate bias and input power can be studied.This study helps in making better linear RF power amplifiers for future wireless technology.
Publications :
 1.The manuscript titled "Prediction of IMD behaviour in LDMOS transistors amplifiers using a physics-based large signal model" has been accepted for poster presentation at the 3rd IEEE International Conference on Emerging Electronics - (ICEE - 2016), IIT Bombay.
• Ankit Shukla (Dual Degree)
Date of Joining in IIT Madras :    23rd July 2012
Research Area :"Electrical Engineering"
Brief description of work: Computational Nanoelectronics - Modeling of Silicon Nanowire Transistor by solving Poisson's equation and single electron Schrodinger's equation. Modelling transport(both ballistic and diffusive) using the Non-equilibrium Greens function (NEGF) method. Diffusive transport through Buttiker's probe method. Modelling of self-heating effects in a SiNWTs.
• Suresh Balanethiram (Ph.D)
UG Course : B.E (Electronics and Communication Engineering)
Year of Graduation :   2009
PG degree : M.Tech (VLSI Design)
Year of Graduation :   2011
University : Karunya University, Coimbatore, Tamilnadu.
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Date of joining in IIT Madras :   21st December 2011
Research Area :    "Microelectronics"
Brief description of work: "Analysis and modeling of electrothermal effects in silicon-germanium heterojunction bipolar transistors"
Aggressively scaled modern silicon-germanium heterojunction bipolar transistors (SiGe HBTs) are suitable for high-speed circuit applications in the (sub - THz) range.  However, in order to achieve this high speed,devices require to operate at high current densities that generate self-heating and subsequently pose a reliability threat.  These thermal issues are made worse by the presence of shallow and deep trench isolations which inhibit the lateral heat diffusion thereby limiting the overall heat-flow volume. Positive electro-thermal feedback of the transistors realized in such technology eventually increases the base-collector junction temperature as well as the thermal resistance of the device. We work on accurate modeling of the electro-thermal effect to facilitate reliable circuit design at high current densities.
Publications :

1.  Suresh Balanethiram, Rosario D'Esposito, Anjan Chakravorty, Sebastien Fregonese and Thomas Zimmer, "Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs." IEEE Transactions on Electron Devices (Accepted).
2.  Suresh Balanethiram, Rosario D'Esposito, Anjan Chakravorty, Sebastien Fregonese, Didier Celi and Thomas Zimmer, "Efficient Modeling of Distributed Dynamic Self-Heating and Thermal Coupling in Multi-finger SiGe HBTs." IEEE Trans. on Electron Devices, 63(9), pp. 3393-3398, 2016.
3.  Anjan Chakravorty, Rosario D'Esposito, Suresh Balanethiram, Sebastian Fregonese and Thomas Zimmer, " "Analytic Estimation of Thermal Resistance in HBTs." IEEE Trans. on Electron Devices, 63(8), pp. 2994-2998, 2016.
4.  Suresh Balanethiram, Anjan Chakravorty, Rosario D'Esposito, Sebastien Fregonese and Thomas Zimmer, "Extracting FEOL and BEOL Components of Thermal Resistance in SiGe HBTs." IEEE International Conference on Emerging Electronics -(ICEE), Mumbai, 2016.
5.  Suresh Balanethiram, Anjan Chakravorty, Rosario D'Esposito, Sebastian Fregonese and Thomas Zimmer, "An Improved Scalable Self-Consistent Iterative Model for Thermal Resistance in SiGe HBTs." IEEE Bipolar/Bi-CMOS Ciruits and Technology Meeting (BCTM), NJ, USA, Sep-2016.
6.  Suresh Balanethiram, Anjan Chakravorty, Rosario D'Esposito, Sebastien Fregonese, and Thomas Zimmer, "Efficient Modeling of Static Self-Heating and Thermal Coupling in Multi-finger SiGe HBTs." IEEE Bipolar/Bi-CMOS Circuits and Technology Meeting (BCTM), Boston, USA, Oct-2015.
7.  Suresh Balanethiram and Anjan Chakravorty, "Analysis of Electro-Thermal Instability in Bipolar Transistors." IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Singapore, June-2015.
• Sudheer.N.V(MS)
Research Area : Investigation and modeling of CNTFET from NEGF
Brief description of work: A rigorous investigation of NEGF simulated nano-FET structure leads to estimation of accurate charge components and currents. Computationally less expensive self-consistent model is successfully applied to obtain the drain-source current and (trans-) conductances. The model agreement with NEGF data proves suitability of the implemented model. Charge based analysis of NEGF data results into non-reciprocal capacitances, for which suitable model is under development .
Publications :
1. N. V. Sudheer and A. Chakravorty, “Regional Approach to Model Charges and Capacitances of Intrinsic Carbon Nanotube Field Effect Transistors”, Journal of Computational Electronics, Springer, DOI 10.1007/s10825-012-0391-1, 2012.
• Noel Augustine (MS)
UG Course :  B.Tech
College : College of Engineering, Chenganur.
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Research Area : Modeling of NQS Effects in SiGe HBTs
Brief description of work: A compact model for vertical NQS effects with improved accuracy and speed is developed and tested against DEVICE simulation data. Model is implemented in Verilog-A.
Publications :
1. N. Augustine, K. Kumar, A. Bhattacharyya, T. Zimmer, and A. Chakravorty, “Modeling Non-Quasi-Static Effects in SiGe HBTs Using Improved Charge Partitioning Scheme”, IEEE Trans. Electron Devices, vol. 59, pp. 2542-2545, 2012.
2. N. Augustine and A. Chakravorty, “Modeling Minority Charge Partitioning Factor in SiGe HBTs Using Full Regional Approach”, Proc. (abstract) of 5th International Conf. on Computers and Devices for Communication, EDM-15, 2012.
3. N. Augustine, K. Kumar, A. Bhattacharyya, T. Zimmer, and A. Chakravorty, “Efficient Models for Non-Quasi-Static Effects and Correlated Noise in SiGe HBTs”, Proc. IEEE International Conf. on Electron Devices and Solid-State Circuits, pp. 1-4, 2012.
4. N. Augustine, K. Kumar, A. Chakravorty, “Applicability of Partition Charge Based Approach for Modeling Non-Quasi-Static Effects in SiGe HBTs”, Proc. (abstract) of 16th International Workshop on the Physics of Semiconductor Devices, MS P.07, pp. 117, 2011.
• Jobymol Jacob (Ph.D)
UG Course :  B.Tech (Applied Electronics & Instrumentation)
College : College of Engineering, Trivandrum.
Year of Graduation :    1992
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PG Course :   M.Tech (Electronics)
University : University of Science & Technology
Year of Graduation :     2003
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Date of Joining in IIT Madras :    11th July 2011
Research Area : "Compact Modeling of Non-Quasi-Static Effects in SiGe HBTs"
Brief description of work: Working on " Non-Quasi-Static(NQS) effect observed in SiGe HBTs". Physics based investigation and modeling from large-signal and small signal prospective is being carried out. Verilog-A implementation is being tested against numerical device simulation(MEDICI) results
Publications :
1.  J. Jacob, A. DasGupta, A. Chakravorty, “Transient Charge-Based Model for SiGe HBTs”, Int. Conf. on Emerging Trends in Electronic and Photonic Devices and Systems, pp. 62-65, 2009.
2.  J. Jacob, A. DasGupta, M. Schroter, A. Chakravorty, “Modeling Non-Quasi-Static Effects in SiGe HBTs”, IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1559-1566, 2010.
3. J. Jacob, A. DasGupta, N. DasGupta, A. Chakravorty, “Analysis of LCR network for modeling non-quasi-static effects in SiGe HBTs”, Proc. (abstract) of 15th International Workshop on the Physics of Semiconductor Devices, pp. 173, 2009.
4. J. Jacob, A. Dasgupta and A. Chakravorty, “Physics Based Modeling of Non-Quasi-static Effects in SiGe HBTs ”, Proc. Second Int. Workshop on Electron Devices and Semiconductor Technology (IEDST), pp. 1-4, DOI 10.1109/EDST.2009.5166125, 2009.
• Kamesh Kumar (Ph.D)
U.G.Course :   B.E (Electronics and Communications Engineering)
University : CITM, MDU Rohtak.
Year of Graduation :   2001

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P.G. Course : M.Tech (Micro-electronics)
University : Punjab University, Chandigarh.

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Date of Joining in IIT Madras :   20th July 2007
Research Area :  "Microelectronics"
Brief description of work: "Compact Modeling of high frequency noise in Si-Ge Heterojunction Bipolar transistors".
Publications :
1. K. Kumar, A. Chakravorty, G. G. Fischer and C. Wipf, "Graded applications of NQS theory for modeling correlated noise in SiGe HBTs," IEEE Transactions on Electron Devices, 62(8), pp. 2384-2389, 2015.
2. N. Augustine, K. Kumar, A. Bhattacharya, T. Zimmer and A. Chakravorty, "Modeling non-quasi-static effects in SiGe HBTs using improved charge partitioning scheme," IEEE Transactions on Electron Devices, 59(9), pp. 2542-2545, 2012.
3. K. Kumar and A. Chakravorty, "Modeling collector current noise PSD of SiGe HBT including self-heating (SH) and non-quasi-static (NQS) effects", Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 2.2, pp. 1-4, 2012.
4. N. Augustine, K. Kumar, A. Bhattacharya, T. Zimmer and A. Chakravorty, "Efficient models for non-quasi-static effects and correlated noise in SiGe HBTs," Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on, pp. 1-4, 2012.
5. K. Kumar and A. Chakravorty, "Modeling high-frequency noise in SiGe HBTs using delayed minority charge", Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 10.4, pp. 183-186, 2011.
6. N. Augustine, K. Kumar and A. Chakravorty, "Applicability of partition charge based approach for modeling non-quasi-static effects in SiGe HBTs", International Workshop on The Physics of Semiconductor Devices (IWPSD), 2011.
7. K. Kumar and A. Chakravorty, "Physics based modeling of RF noise in SiGe HBTs", Electron Devices and Semiconductor Technology (IEDST). 2nd International Workshop on, pp. 1-4, 2009.

Thesis Submitted :   "Yes"
Year of Graduation :    "2016"

• Venkata narayana rao (Ph.D)
Research Area :
Brief description of work:
Publications :
1. Venkata Narayana Rao Vanukuru, Vamsi Krishna Velidi, Anjan Chakravorty, “60 GHz millimeter-wave compact TFMS bandstop filter using transversal resonator in 0.18μm CMOS technology”, 2014 IEEE International Microwave and RF Conference (IMaRC), pp. 248 - 250, 2014.
2. Venkata Narayana Rao Vanukuru, Anjan Chakravorty, “High efficiency millimeter-wave stacked two turn transformer using only top two thick metals”, 2014 IEEE International Microwave and RF Conference (IMaRC), pp. 251-254, 2014.
3. Venkata Narayana Rao Vanukuru, Nagasatish Godavarthi, Anjan Chakravorty, “Miniaturized millimeter-wave narrow bandpass filter in 0.18 μm CMOS technology using spiral inductors and interdigital capacitors”, 2014 International Conference on Signal Processing and Communications (SPCOM), pp. 1-4, 2014.
4. Venkata Narayana Rao Vanukuru, Anjan Chakravorty, “Integrated layout optimized high-g inductors on high-resistivity SOI substrates for RF front-end modules”, 2014 International Conference on Signal Processing and Communications (SPCOM), pp. 1-5, 2014.
• Ujwal Radhakrishna (DD/M.Tech.)
Research Area : Modeling of Currents SOI-LDMOS Transistors
Brief description of work: A compact model for static operation of LDMOSFETs including impact ionization, self-heating and snap back effects is developed and implemented in Verilog-A. The developed model shows high level accuracy against MEDICI simulation data.
• Prasad Sarangapani (DD/M.Tech.)
Research Area : Modeling of Charges in SOI-LDMOS Transistors
Brief description of work: A compact model for dynamic operation of LDMOSFETs is developed and implemented in Verilog-A. The developed model shows high level accuracy against MEDICI simulation data.
• Siddharth.K(Dual Degree)
Research Area : Compact Modeling of CNTFET
Brief description of work: A regional charge analysis to model internal CNFET is carried out by introducing an effective channel length, finding accurate partitioning point using distributed capacitance, and calculating the partition factor to obtain all the charge components, QG, QD and QS. Both large (IDS, QG, QD), and small signal (gm, CGD, CDG) characteristics are investigated. The charge-based approach provides expected non-reciprocal trans-capacitances
• Aritra Dey(MS)
Research Area : Compact Modeling of DGMOSFETs
Brief description of work: Analytical model for surface potential for bulk MOSFET and potential based model for DGMOSFET were carried out. Both symmetric and asymmetric DGMOSFET were investigated. Model equations were proposed for large signal current, charge components as well as corresponding small-signal quantities
• M.Sumathi(M.Tech)
Research Area : High Current Effects In Bipolar Transistors
Brief description of work: Worked on high current effects in SiGe HBTs. One dimensional intrinsic HBT structure was simulated using MEDICI and its behavioral effects was investigated at high current regime, where electric field in the collector significantly changes its behavior. This leads to change in BC junction capacitances making it transfer current dependent unlike only its voltage dependent behavior. Cases of fully and partially depleted collector were investigated and corresponding modeling work was carried out
• Lekshmi.T (M.Tech)
Research Area : Compact Modeling of LDMOS
Brief description of work: HV LDMOS structure was thoroughly analyzed using MEDICI simulation. Regions of velocity saturation at different bias voltages were identified and physical basis was addressed behind the bias dependent effects. The quasi-saturation effect was modeled successfully and model verification was carried out. Thermal and electro-thermal modeling is initiated along with the investigation on geometry scalability
• Amit Mittal (DD/M.Tech.)
Research Area : Compact Modeling of LDMOS
Brief description of work: Low and high voltage LDMOS structure was simulated and model investigation was carried out using MM20 model. A successful verilog-A implementation was carried out and model verification was obtained with the numerical simulation. HV LDMOS on SOI was given importance and quasi-saturation effect modeling was initiated
• Abbay.B(B.Tech)
Compact Modeling of Noise in SiGe HBTs
Brief description of work: Worked on SiGe HBT noise modeling and VA implementation using VBIC model. Experimental data was obtained from IHP microelectronics for three different types (high speed, high voltage and medium speed) of HBTs. Model investigation was carried out including DC, AC and noise behavior. Noise correlation was studied and addressed in the implemented model
• Max Haferlach(under DAD Program)
Research Area : Compact Modeling of CNTFET
Brief description of work: A large-signal model was developed for intrinsic CNTFET by formulating suitable charge and current expressions. Investigation of extrensic model was also carried out. Model was implementated in Verilog-A and verifed with numerical simulation data. For the internal FET, analytical expression for small-signal Y-parameters were derived and the results were found in agreement with the implemented model simulation