As technologies and their power supply voltages scale down, it becomes more difficult to maintain the accuracy of data converters. At the same time, increasing complexity of systems on chip demands data converters with lower power consumption and higher accuracy. We are investigating a variety of techniques such as predistortion and self calibration to lower the power consumption and improve the accuracy.

• V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, “ A Distortion Compensating Flash Analog to Digital Conversion Technique,” IEEE Journal of Solid State Circuits. September 2006. (paper)
• S. Murali and S. Pavan,“ Rapid Simulation of Current Steering DACs using Verilog-A,” Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2006, San Jose, September 2006.(paper)
• S. Pavan, P. Easwaran and C. Srinivasan,“System Level Aspects of Analog-to-Digital Converter Designs,” International Conference on VLSI Design, Hyderabad, India, January 2006. (slides)
• G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, “ A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ”, Proceedings of the Custom Integrated Circuits Conference, May 2001. (paper)
• K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process”, IEEE Journal of Solid State Circuits, December 2000.
• K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “ A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode”, International Solid State Circuits Conference, February 2000. (paper)
• K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “ A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS”, Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000.