P. Kumar and N. Krishnapura, “Signal-Strength Detector Based on CMOS-Inverter Supply Current,” IEEE Solid-State Circuits Letters, doi: 10.1109/LSSC.2023.3307361.

Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura, “Bandpass filter and oscillator ICs with THD < -140dBc at 10Vppd for testing high-resolution ADCs,” 2023 International Solid-State Circuits Conference, San Francisco, USA, Feb. 2023. Accepted for presentation. doi: 10.1109/ISSCC42615.2023.10067771.

S. Ramprasath, M. Madhusudan et al., “A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” ACM Transactions on Design Automation of Electronic Systems, doi: 10.1145/3580477.

J. Poojary, S. Ramprasath et al., “Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Diego, USA, June 2023. doi: 10.1109/RFIC54547.2023.10186141.

R. S. A. Kumar, N. Krishnapura and P. Banerjee, “Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier,” IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, doi: 10.1109/JSSC.2022.3171790.

K. M. Vithagan, V. Sundaresha and J. Viraraghavan, “Geometric Programming Approach to Glitch Minimization via Gate Sizing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3207970.

A. F. Davidson and J. Viraraghavan, “Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection,” in IEEE Transactions on Education, 2022, doi: 10.1109/TE.2022.3192624.

S. Ramprasath, M. Madhusudan et al., “Analog/Mixed-Signal Layout Optimization using Optimal Well Taps,” International Symposium on Physical Design, Virtual Event Canada, Apr. 2022. doi: 10.1145/3505170.3506728

T. Dhar, S. Ramprasath et al., “A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement,” Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, Mar. 2022. doi: 10.23919/DATE54114.2022.9774621

R. S. A. Kumar, N. Krishnapura and P. Banerjee, “Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier,” IEEE Journal of Solid-State Circuits. Early access.

T. Raviteja and S. Pavan, “Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback,” IEEE Transactions on Circuits and Systems II: Express Briefs, to appear.

U Mukherjee, T Halder, A Kannan, S Ghosh, S Pavan,“A 28.5 µW All-Analog Voice-Activity Detector,” Proceedings of the IEEE International Symposium on Circuits and Systems, 2021.

S. Manivannan and S.Pavan, “A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth,” IEEE Solid-State Circuits Letters, March 2021.

S. Pavan, T. Halder and A. Kannan, “Continuous-Time Incremental Delta-Sigma Modulators with FIR Feedback,” IEEE Transactions on Circuits and Systems I: Regular Papers, August 2021.

S. Pavan and H. Shibata, “Continuous-Time Pipelined ADCs : A Mini-Tutorial,” IEEE Transactions on Circuits and Systems II: Express Briefs, March 2021.

R. S. A. Kumar and N. Krishnapura, “Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter,” IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3094679.

A. Bhat and N. Krishnapura, “A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G_m for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3096843.

A.Baluni and S.Pavan,“Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback,”IEEE Journal of Solid-State Circuits, vol. 56, no. 4, Apr. 2021.

A. Santra and Q. A. Khan, “A High Gain, Low Offset Time-Based Operational Amplifier for Capacitive Loads with 36MHz UGB and 70µA Quiescent Current,” 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 432-436, doi: 10.1109/MWSCAS47672.2021.9531892.

S. Guddanti and Q. A. Khan, “A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.

A. Chitnis, R. Chauhan, D. Kaur and Q. Khan, “A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT,” 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021.

A. Nallathambi, S. Sen, A. Raghunathan, N. Chandrachoodan, “Probabilistic spike propagation for efficient hardware implementation of spiking neural networks”, Frontiers in Neuroscience, vol 15, 2021

B. N. G. Koneru, N. Chandrachoodan and V. Vasudevan, “A Smoothed LASSO-Based DNN Sparsification Technique,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4287-4298, Oct. 2021

B. Vijayakumar and J. Viraraghavan, “An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401131. (Accepted for poster)

S.Billa,S.Dixit and S.Pavan,“Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator,” IEEE Journal of Solid-State Circuits, vol. 55, no. 11, Nov. 2020.

I. Mondal and N. Krishnapura, “Effects of AC Response Imperfections in True-Time-Delay Lines,” IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2020.3027529.

R.Theertham, P.Kootala, S.Billa and S.Pavan, “Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density,” IEEE Journal of Solid-State Circuits, vol. 55, no. 9, Sept. 2020.

S.Manivannan and S.Pavan,“Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering,” IEEE Transactions on Circuits and Systems I: Regular Papers, October 2020.

R. S. A. Kumar and N. Krishnapura, “Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset,” IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2020.3013691.

Chithra and N. Krishnapura, “A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 1892-1901, June 2020, doi: 10.1109/TCSI.2020.2969977.

G. R., J. D. Bandarupalli, S. Saxena, “A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for presentation).

S. Mukherjee, A. Das, S. Seth, S. Saxena, “An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for presentation).

Apoorva Bhatia, Yogesh Darwhekar, Subhashish Mukherjee, Samuel Martin, Nagendra Krishnapura, “A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for presentation).

Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura, “Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for presentation).

A. D. Carmine, A. Santra, Q. Khan, “A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).

K. Peetala, A. Ranjan, R. Aenkamreddi, Q. Khan, “An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement,” 2020 International Symposium on Circuits and Systems (ISCAS), 17-20 May 2020, Seville, Spain. (Accepted for poster presentation).

S. A. Balagopal and J. Viraraghavan, “Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180925. (Accepted for poster)

M. V. Praveen and N. Krishnapura, “High Linearity Transmit Power Mixers Using Baseband Current Feedback,” IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 272-281, Feb. 2020. doi: 10.1109/JSSC.2019.2945962

A.Baluni and S.Pavan, “A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC,” IEEE Custom Integrated Circuits Conference (CICC), March 2020. (Outstanding Student Paper Award)

H.Shibata,G.Taylor,..,and S.Pavan, “An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter,” IEEE International Solid State Circuits Conference (ISSCC), February 2020.

S Panchapakesan, Z Fang, N Chandrachoodan, “EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA”, IEEE 28th Intl. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2020

G Mitra, P K Vairam, Patanjali S., N Chandrachoodan, V Kamakoti, “Depending on HTTP/2 for Privacy? Good Luck!”, 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2020

S Rangachari, N Chandrachoodan, “Energy Reduction in Turbo Decoding through Dynamically Varying Bit- Widths”, International Symposium on Circuits and Systems (ISCAS), 2020

G Vadakkeveedu, K Veezhinathan, N Chandrachoodan, S Potluri, “Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips”, IET Comp. & Dig. Techniques 14 (3), 122-131, 2020

C Dharmaraj, V Vasudevan, N Chandrachoodan, “Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders”, ACM Transactions on Embedded Computing Systems (TECS) 20 (2), 1-25, 2020

C Dharmaraj, V Vasudevan, N Chandrachoodan, “Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders”, IET Computers & Digital Techniques 15 (2), 97- 111, 2020

R. S. A. Kumar and N. Krishnapura, “A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter,” ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), Cracow, Poland, 2019, pp. 365-368. doi: 10.1109/ESSCIRC.2019.8902610

N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, “Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3531-3543, Sept. 2019. doi: 10.1109/TCSI.2019.2926143

S. Kumar, R. Goroju, D. K. Bhat, K. S. Rakshitdatta and N. Krishnapura, “Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3393-3401, Sept. 2019. doi: 10.1109/TCSI.2019.2926927

Shanthi Pavan and Raviteja Theertham, “Improved offline calibration of DAC errors in Delta Sigma data converters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp. 1618-1622, Oct. 2019. doi: 10.1109/TCSII.2019.2921777

Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, and Shanthi Pavan, “Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezo Electric Energy Harvesting,” IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2590-2600, Sept. 2019. doi: 10.1109/JSSC.2019.2917158

Raviteja Theertham, Prasanth Kootala, Sujith Billa, and Shanthi Pavan, “A 24mW chopped CTDSM achieving 103.5dB SNDR and 107.5dB DR in a 250kHz bandwidth,” 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019, pp. C226-C227. doi: 10.23919/VLSIC.2019.8778026

Raviteja Theertham and Shanthi Pavan, “Unified analysis, modeling, and simulation of chopping artifacts in continuous-time delta-sigma converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2831-2842, Aug. 2019. doi: 10.1109/TCSI.2019.2907167

Kishalay Dutta, Vinod Menezes and Shanthi Pavan, “Analysis and design of cyclic switched-capacitor DC-DC converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3227-3237, Aug. 2019. doi: 10.1109/TCSI.2019.2907309

Saravana Manivannan and Shanthi Pavan, “Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702763

Shanthi Pavan, “Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702129

Shanthi Pavan, “An alternative approach to Bode's Noise Theorem,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 738-742, May 2019. doi: 10.1109/TCSII.2019.2907860

Abirmoya Santra, Angelo De Carmine, Guttha Venkata Sesha Rao, Qadeer A. Khan, “A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-4. doi: 10.1109/ISCAS.2019.8702457

Chithra and Nagendra Krishnapura, “Static Phase Offset Reduction Technique for Delay Locked Loops,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702613

Chithra and Nagendra Krishnapura, “Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design,” 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), Hyderabad, India, 2019, pp. 1-6. doi: 10.1109/MOS-AK.2019.8902447

Abhishek Bhat and Nagendra Krishnapura, “A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 412-414. doi: 10.1109/ISSCC.2019.8662502

Abirmoya Santra and Qadeer A. Khan, “A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-forward Compensation,” 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, NCR, India, 2019, pp. 36-40. doi: 10.1109/VLSID.2019.00025

B. Xiao et al., “An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier,” 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, pp. 39-42.

Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan, “A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits”, IEEE Trans. VLSI Syst. 27(2): 376-386 (2019)

Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, “A Dual Slope LVDT-to-Digital Converter,” IEEE Sensors Journal, vol. 19, no. 3, pp. 868-876, 1 Feb.1, 2019. doi: 10.1109/JSEN.2018.2878883

Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, “A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 6, pp. 919-923, June 2019. doi: 10.1109/TCSII.2018.2873053

Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, “Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2873-2883, Dec. 2018. doi: 10.1109/TVLSI.2018.2861818

Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, “A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 43-53, Jan. 2019. doi: 10.1109/TCSI.2018.2858197

G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna, “Performance Analysis of Oscillator Based Read-out Circuit for LVDT,” IEEE Transactions on Instrumentation and Measurement, vol. 68, no. 4, pp. 1080-1088, April 2019. doi: 10.1109/TIM.2018.2858038

R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, “Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3651-3661, Nov. 2018. doi: 10.1109/TCSI.2018.2854707

Abhishek Bhat and Nagendra Krishnapura, “On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 162-166, Feb. 2019. doi: 10.1109/TCSII.2018.2842101

S.Manivannan and S.Pavan, “Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3207-3215, Oct. 2018. doi: 10.1109/TCSI.2018.2826443

S.Pavan and E.Klumperink, “Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3267-3278, Oct. 2018. doi: 10.1109/TCSI.2018.2816342

S. Javvaji, V.Singhal, V.Menezes and S.Pavan, “Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting,” ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, 2018, pp. 42-45. doi: 10.1109/ESSCIRC.2018.8494272

A. Kumar and S. Aniruddhan,“A 2.5GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3174-3185, Oct. 2018. doi: 10.1109/TCSI.2018.2809924

S. Pavan, “Improved Chopping in Continuous-Time Delta–Sigma Converters Using FIR Feedback and ${N}$ -Path Techniques,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 552-556, May 2018. doi: 10.1109/TCSII.2018.2820017

S. Pavan and S. Baskaran, “What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-5. doi: 10.1109/ISCAS.2018.8351141

P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham, “Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-5. doi: 10.1109/ISCAS.2018.8351140

A. Thakkar, S. Theertham, P. Mirajkar, J. C. Goyal and S. Aniruddhan, “A 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-5. doi: 10.1109/ISCAS.2018.8351527

A. Kumar, R. K. Ganti and S. Aniruddhan, “A Same-Channel Full-Duplex Receiver Using Direct RF Sampling,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4. doi: 10.1109/ISCAS.2018.8351676

Q. A. Khan, S. Saxena and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-5. doi: 10.1109/ISCAS.2018.8351598

S. Pavan, “Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters,” 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-8. doi: 10.1109/CICC.2018.8357084

S. Manivannan and S. Pavan, “A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR,” 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4. doi: 10.1109/CICC.2018.8357089

S. Pavan, “Practical design and simulation techniques for continuous-time ΔΣ converters,” 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-81. doi: 10.1109/CICC.2018.8357104

I. Mondal and N. Krishnapura, “Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2703-2714, Sept. 2018. doi: 10.1109/TCSI.2018.2799080

A. Bhat and N. Krishnapura, “Low $1/f^{3}$ Phase Noise Quadrature LC VCOs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2127-2138, July 2018. doi: 10.1109/TCSI.2017.2782247

S. Pavan and E. Klumperink, “Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 5, pp. 1469-1480, May 2018. doi: 10.1109/TCSI.2017.2754342

P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham, “Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 589-593, March 2018. doi: 10.1109/TVLSI.2017.2769709

A. Jain and S. Pavan, “Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 2, pp. 434-443, Feb. 2018. doi: 10.1109/TCSI.2017.2740287

Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata and Subramanian Iyer “80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity,” IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 949-960, March 2018. doi: 10.1109/JSSC.2017.2784760

Q. A. Khan, S. Kim and P. K. Hanumolu, “Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers,” 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, 2018, pp. 226-231. doi: 10.1109/VLSID.2018.67

D. Celia, Vinita Vasudevan, Nitin Chandrachoodan, “Probabilistic Error Modeling for Two-part Segmented Approximate Adders”, Intl. Symp. On Circ & Systems (ISCAS) 2018.

Karthikeyan Natarajan, Nitin Chandrachoodan, “Lossless Parallel Implementation of a Turbo Decoder on GPU”, High Performance Computing (HiPC) 2018.

D. Celia, Vinita Vasudevan, Nitin Chandrachoodan, “Optimizing power-accuracy trade-offi in approximate adders”, Design, Automation, and Test in Europe (DATE) 2018.

Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Hairong Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil and Shanthi Pavan, “A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD,” IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3219-3234, Dec. 2017. doi: 10.1109/JSSC.2017.2747128

Gaurav Agrawal and Sankaran Aniruddhan, “A Modified Bias Scheme for High-Gain Low-Noise Folded Cascode OTAs”, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, 2017, pp. 1-4. doi: 10.1109/EDSSC.2017.8126531

Ramakrishna Avula and Sankaran Aniruddhan, “Low-Voltage 0.5.3GHz Radio Receiver for Multiband Cellular Applications,” 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, 2017, pp. 1-2. doi: 10.1109/EDSSC.2017.8126519

Arpan Thakkar, Apoorva Bhatia, Vikram Sharma, Srinivas Theertham and Sankaran Aniruddhan, “A 4-Port Inductor based Compact Dual-core VCO with Improved Phase Noise Performance,” 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, 2017, pp. 1-4. doi: 10.1109/EDSSC.2017.8126521

Arpan Thakkar, Srinivas Theertham, Sankaran Aniruddhan, Peeyoosh Mirajkar and Jagdish Chand Goyal, “A 3.9–4.5GHz class-C VCO with accurate current injection based on capacitive feedback,” 2017 12th European Microwave Integrated Circuits Conference (EuMIC), Nuremberg, 2017, pp. 224-227. doi: 10.23919/EuMIC.2017.8230700

Sujith Billa, Amrith Sukumaran and Shanthi Pavan, “Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping,” IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2350-2361, Sept. 2017. doi: 10.1109/JSSC.2017.2717937

Shanthi Pavan and Eric Klumperink,“Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and $N$-Path Filters Using the Adjoint Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 10, pp. 2714-2725, Oct. 2017. doi: 10.1109/TCSI.2017.2703579

Neha Sinha, Mansour Rachid, Shanthi Pavan and Sudhakar Pamarti,“Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components,” IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2009-2025, Aug. 2017. doi: 10.1109/JSSC.2017.2697412

Shanthi Pavan, “Analysis of chopped integrators and its application to continuous-time delta-sigma modulator design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 8, pp. 1953-1965, Aug. 2017. doi: 10.1109/TCSI.2017.2682884

Saravanan K. and S. Aniruddhan, “Area Efficient Low Power Crystal Oscillator with Automatic Amplitude Control,” 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, 2017, pp. 731-734. doi: 10.1109/MWSCAS.2017.8053027

Arjun Nadh, Joseph Samuel, Ankit Sharma, Sankaran Aniruddhan, and Radha Krishna Ganti, “A Taylor Series Approximation of Self-Interference Channel in Full-Duplex Radios,” IEEE Transactions on Wireless Communications, vol. 16, no. 7, pp. 4304-4316, July 2017. doi: 10.1109/TWC.2017.2696938

Imon Mondal and Nagendra Krishnapura, “A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2180-2193, Aug. 2017. doi: 10.1109/JSSC.2017.2693229

Sumit Kumar and Nagendra Krishnapura, “Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4. doi: 10.1109/ISCAS.2017.8051001

Shanthi Pavan, “On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4. doi: 10.1109/ISCAS.2017.8050952

Vinodhini G., Sankaran Aniruddhan, Boby George, Dhurga Devi J. and Ramakrishna P.V., “A Simple and Efficient Oscillator Based Read-out Scheme for LVDT,” 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Turin, 2017, pp. 1-5. doi: 10.1109/I2MTC.2017.7969655

Sreenivasa Mallia S, Sreeram NS, Sudhir Adinarayana, and Sankaran Aniruddhan, “A Self-Powered 50-Mb/s OOK Transmitter for Optoisolator LED Emulation,” IEEE Journal of Solid-State Circuits, vol. 52, no. 3, pp. 678-687, March 2017. doi: 10.1109/JSSC.2016.2633577

Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, “25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 434-435. doi: 10.1109/ISSCC.2017.7870447

R. S. Ashwin Kumar and Nagendra Krishnapura, “A Low Power Multi-channel Input Delta-Sigma ADC without Reset,” 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 9-14. doi: 10.1109/VLSID.2017.85

Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan, “Scenario-Aware Dynamic Power Reduction Using Bias Addition”, IEEE Transactions on VLSI Systems, vol. 25, no. 2, Feb 2017

Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti, “An Asymmetric 2.4 GHz Directional Coupler Using Electrical Balance,” IEEE Microwave and Wireless Components Letters, vol. 26, no. 12, pp. 990-992, Dec. 2016. doi: 10.1109/LMWC.2016.2623252

Gaurav Agrawal, Sankaran Aniruddhan, and Radha Krishna Ganti, “A Compact Mixer-First Receiver With >24 dB Self-Interference Cancellation for Full-Duplex Radios,” IEEE Microwave and Wireless Components Letters, vol. 26, no. 12, pp. 1005-1007, Dec. 2016. doi: 10.1109/LMWC.2016.2623253

Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata and Subramanian S. Iyer, “A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access,” IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873

Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer, “80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity,” 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. doi: 10.1109/VLSIC.2016.7573462

Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, “A 12.5 mW, 11.1 $\text{nV}/\sqrt{\text{Hz}}$, −115 dB THD, $ < 1\ \mu\text{s}$ Settling, 18 bit SAR ADC Driver in 0.6 $\mu\text{m}$ CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 5, pp. 443-447, May 2016. doi: 10.1109/TCSII.2015.2504024

Abhishek Bhat and Nagendra Krishnapura, “A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2070-2073. doi: 10.1109/ISCAS.2016.7538986

Shanthi Pavan, “Continuous-Time Delta Sigma Modulators with Dual Switched Capacitor Resistor DACs,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 69-72. doi: 10.1109/ISCAS.2016.7527172

Aparna Girija and Aniruddhan S, “A Compact Dual-Band 5dBm RF Power Amplifier for Cellular Applications,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2118-2121. doi: 10.1109/ISCAS.2016.7538998

A. Sukumaran and S. Pavan, “Design of Continuous-Time $\Delta \Sigma $ Modulators With Dual Switched-Capacitor Return-to-Zero DACs,” IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1619-1629, July 2016. doi: 10.1109/JSSC.2016.2542200

A. Jain and S. Pavan, “A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback,” 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. doi: 10.1109/VLSIC.2016.7573466

S. Pavan and R. Rajan, “Design Considerations for Filtering Delta Sigma Converters”, Proceedings of the Workshop on Advanced Analog Circuit Design, 24th-27th April 2016, Villach, Austria. https://doi.org/10.1007/978-3-319-41670-0_4

Anandha Ruban T T, Preetam Tadeparthy, Sankaran Aniruddhan, Vikram Gakhar, and Muthusubramanian Venkateswaran, “Optimal dynamic phase add/drop mechanism in multiphase DC-DC buck converters,” 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, USA, 20-24 March 2016. doi: 10.1109/APEC.2016.7468124

S. Billa, A. Sukumaran and S. Pavan, “15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 276-277. doi: 10.1109/ISSCC.2016.7418014

K. Singh and S. Pavan, “A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition,” 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 230-235. doi: 10.1109/VLSID.2016.21

S. Pavan and N. Krishnapura, “Demystifying Time Varying Circuits and Systems,” 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 17-18. doi: 10.1109/VLSID.2016.135

R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, “A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 283-295, Feb. 2017. doi: 10.1109/TCSI.2016.2609855

A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,” IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. doi: 10.1109/JSSC.2016.2557807

G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition,” IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016. doi: 10.1109/JSSC.2015.2497963

G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu, “23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 398-399. doi: 10.1109/ISSCC.2016.7418075

Celia Dharmaraj and Nitin Chandrachoodan, “Guided Multilevel Approximation of Less Significant Bits for Power Reduction”, Intl. Symposium on VLSI Design and Test (VDAT), 2016.

Amit Salaskar, Nitin Chandrachoodan, “FFT/IFFT implementation using Vivado HLS”, Intl. Sym. On VLSI Des. & Test (VDAT) 2016.

J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan, “Next-Generation Delta-Sigma Converters: Trends and Perspectives,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 5, no. 4, pp. 484-499, Dec. 2015. doi: 10.1109/JETCAS.2015.2502164

S. Potluri, A. S. Trinadh, S. Babu, V. Kamakoti and N. Chandrachoodan, “DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-on-Shift At-Speed Testing”, ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 1, Nov 2015

Chaitanya Peddawad, Aman Goel, B. Dheeraj, Nitin Chandrachoodan,“iitRACE: A Memory Effiicient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal”, ICCAD 2015.

Amrith Sukumaran and Shanthi Pavan, “A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC,” ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, 2015, pp. 217-220. doi: 10.1109/ESSCIRC.2015.7313866

Imon Mondal and Nagendra Krishnapura, “Gain enhanced high frequency OTA with on-chip tuned negative conductance load,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 2085-2088. doi: 10.1109/ISCAS.2015.7169089

Sandeep Krishnan and Shanthi Pavan, “A 10 Gbps eye opening monitor in 65nm CMOS,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 3028-3031. doi: 10.1109/ISCAS.2015.7169325

Naga Rajesh and Shanthi Pavan, “Programmable analog pulse shaping for ultra-wideband applications,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 461-464. doi: 10.1109/ISCAS.2015.7168670

Rakshitdatta K. S. and Nagendra Krishnapura, “On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback,” 2015 28th International Conference on VLSI Design, Bangalore, 2015, pp. 244-248. doi: 10.1109/VLSID.2015.47

Imon Mondal and Nagendra Krishnapura, “Accurate Constant Transconductance Generation without Off-Chip Components,” 2015 28th International Conference on VLSI Design, Bangalore, 2015, pp. 249-253. doi: 10.1109/VLSID.2015.48

T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS,” 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3. doi: 10.1109/ISSCC.2015.7062927

R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method,” IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 882-895, April 2015. doi: 10.1109/JSSC.2014.2385756

A. Elkholy, S. Saxena, and P. K. Hanumolu, “A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter,” 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015, pp. 1-4. doi: 10.1109/CICC.2015.7338376

S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi and P. K. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C352-C353. doi: 10.1109/VLSIC.2015.7231320

T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly and P. K. Hanumolu, “3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS,” 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3. doi: 10.1109/ISSCC.2015.7062927

S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,” IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. doi: 10.1109/JSSC.2015.2456884

S. J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “High Frequency Buck Converter Design Using Time-Based Control Techniques,“ IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 990-1001, April 2015. doi: 10.1109/JSSC.2014.2378216

S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski and P. K. Hanumolu, “12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS,” 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3. doi: 10.1109/ISSCC.2015.7063003

Debasish Behera and Nagendra Krishnapura, “A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter,” ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venice Lido, 2014, pp. 415-418. doi: 10.1109/ESSCIRC.2014.6942110

R. Rajan and S.Pavan, “Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering,” IEEE Journal of Solid-State Circuits, vol. 49, no. 10, pp. 2187-2198, Oct. 2014. doi: 10.1109/JSSC.2014.2345023

A. Sukumaran and S.Pavan, “Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2515-2525, Nov. 2014. doi: 10.1109/JSSC.2014.2332885

S.Pavan and R. Rajan, “Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time $\Delta\Sigma$ Modulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 9, pp. 681-685, Sept. 2014. doi: 10.1109/TCSII.2014.2335414

S.Pavan and R. Rajan, “Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 9, pp. 686-690, Sept. 2014. doi: 10.1109/TCSII.2014.2335393

Nagendra Krishnapura and K. S. Rakshitdatta, “A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2219-2228, Aug. 2014. doi: 10.1109/TCSI.2014.2333681

N. Rajesh and S.Pavan, “Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1800-1814, Aug. 2014. doi: 10.1109/JSSC.2014.2317132

Abhishek Kumar, S. Aniruddhan and Radha Krishna Ganti, “Directional coupler with high isolation bandwidth using electrical balance,” 2014 IEEE MTT-S International Microwave Symposium (IMS2014), Tampa, FL, 2014, pp. 1-3. doi: 10.1109/MWSYM.2014.6848434

Saravanan K and S. Aniruddhan, “Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 1002-1005. doi: 10.1109/ISCAS.2014.6865307

Abhishek Kumar and S. Aniruddhan, “Ground-Bounce Reduction in Narrow-Band RF Front-Ends,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 189-192. doi: 10.1109/ISCAS.2014.6865097

Gaurav Agrawal, S. Aniruddhan and Radha Krishna Ganti, “Multi-band RF time delay element based on frequency translation,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 1368-1371. doi: 10.1109/ISCAS.2014.6865398

S. Pavan, “Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 726-729. doi: 10.1109/ISCAS.2014.6865238

S. Pavan, “Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 6, pp. 1629-1637, June 2014. doi: 10.1109/TCSI.2013.2290846

A. Jain and S. Pavan, “Characterization Techniques for High Speed Oversampled Data Converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 5, pp. 1313-1320, May 2014. doi: 10.1109/TCSI.2014.2309895

R. Rajan and S. Pavan, “29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 478-479. doi: 10.1109/ISSCC.2014.6757520

N. Krishnapura, “Tutorial T6A: Pedagogy of Negative Feedback Circuits,” 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, 2014, pp. 13-13. doi: 10.1109/VLSID.2014.121

S. Saxena, R. K. Nandwana and P. K. Hanumolu, “A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. doi: 10.1109/JSSC.2014.2317142

G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1036-1047, April 2014. doi: 10.1109/JSSC.2013.2296152

R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,” 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. doi: 10.1109/VLSIC.2014.6858446

M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi and P. K. Hanumolu, “A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter,” 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. doi: 10.1109/VLSIC.2014.6858392

A. Elkholy, A. Elshazly, S. Saxena, G. Shu and P. K. Hanumolu, “15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 272-273. doi: 10.1109/ISSCC.2014.6757431

G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly and P. K. Hanumolu, “8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 150-151. doi: 10.1109/ISSCC.2014.6757377

Q. Khan, S. J. Kim; M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW,“ 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2. doi: 10.1109/VLSIC.2014.6858439

Janakiraman V., Pandharpure S.J. and Watts J., (2014) “Statistical Compact Model Extraction for Skewed Gaussian Variations”, “In: Jain V., Verma A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering”. Springer, Cham. paper

S. Pavan, “Systematic Derivation of Well Known Analog Circuits,” 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Visakhapatnam, 2013, pp. 1-12. doi: 10.1109/PrimeAsia.2013.6731167

M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, “Compact silicon biosensor for the clinical range estimation of blood serum triglycéride,” SENSORS, 2013 IEEE, Baltimore, MD, 2013, pp. 1-4. doi: 10.1109/ICSENS.2013.6688212

A. Sukumaran and S. Pavan, “A 280 μW Audio Continuous-Time Modulator with 103 dB DR and 102 dB A-Weighted SNR,” 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013, pp. 385-388. doi: 10.1109/ASSCC.2013.6691063

A. Sukumaran, K. Karanjkar, S. Jhanwar, N. Krishnapura and S. Pavan, “A 1.2 V 285 μA Analog Front End Chip for a Digital Hearing Aid in 0.13μm CMOS,” 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013, pp. 397-400. doi: 10.1109/ASSCC.2013.6691066

N. Krishnapura and Rakshitdatta K. S., “A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions,” Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1-4. doi: 10.1109/CICC.2013.6658427

N. Rajesh and S. Pavan, “A Lumped Component Programmable Delay Element for Ultra-Wideband Beamforming,” Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1-4. doi: 10.1109/CICC.2013.6658475

T.Nandi, K.Boominathan and S.Pavan, “Continuous-Time $\Delta \Sigma $ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC,” IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1795-1805, Aug. 2013. doi: 10.1109/JSSC.2013.2259012

M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, “A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit”, IEEE Sensors Journal, vol. 13, no. 5, pp. 1941-1948, May 2013. doi: 10.1109/JSEN.2013.2245032

A. Jain and S. Pavan, “Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface,” 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, 2013, pp. 1252-1255. doi: 10.1109/ISCAS.2013.6572080

S. Pavan, “A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 2, pp. 81-85, Feb. 2013 doi: 10.1109/TCSII.2012.2235016

S. Pavan, “Simulation Techniques in Data Converter Design,” Tutorial at the International Solid State Circuits Conference (ISSCC), February 2013. paper

S. Saxena, R. K. Nandwana and P. K. Hanumolu, “A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter,” Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1-4. doi: 10.1109/CICC.2013.6658403

R. K. Nandwana, S. Saxena and P. K. Hanumolu, “A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC,” 2013 Symposium on VLSI Circuits, Kyoto, 2013, pp. C156-C157. paper

G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,”A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,“ 2013 Symposium on VLSI Circuits, Kyoto, 2013, pp. C278-C279. paper

Janakiraman Viraraghavan, Shrinivas J. Pandharpure and Josef Watts, “Statistical Compact Model Extraction: A Neural Network Approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp. 1920-1924, Dec. 2012. doi: 10.1109/TCAD.2012.2207955

P. Shettigar and S.Pavan, “Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs,” IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. doi: 10.1109/JSSC.2012.2217871

T. Nandi, K. Boominathan and S.Pavan, ” A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC,“ Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, 2012, pp. 1-4. doi: 10.1109/CICC.2012.6330692

R.S.Rajan and S.Pavan, “Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 524-527. doi: 10.1109/ISCAS.2012.6272081

V. Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N.Nigania “A 16 MHz BW 75 dB DR CT $\Delta\Sigma$ ADC Compensated for More Than One Cycle Excess Loop Delay,” IEEE Journal of Solid-State Circuits, vol. 47, no. 8, pp. 1884-1895, Aug. 2012. doi: 10.1109/JSSC.2012.2196730

A.Jain, N. Muthusubramaniam and S.Pavan, “Analysis and Design of a High Speed Continuous-time $\Delta\Sigma$ Modulator Using the Assisted Opamp Technique,” IEEE Journal of Solid-State Circuits, vol. 47, no. 7, pp. 1615-1625, July 2012. doi: 10.1109/JSSC.2012.2191210

R.S.Rajan and S.Pavan, “Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 524-527. doi: 10.1109/ISCAS.2012.6272081

Nagendra Krishnapura, “Introducing negative feedback with an integrator as the central element,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 2449-2452. doi: 10.1109/ISCAS.2012.6271794

Nagendra Krishnapura, “Synthesis based introduction to opamps and phase locked loops,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 2461-2464. doi: 10.1109/ISCAS.2012.6271798

Sankaran Aniruddhan, “Quadrature generation techniques in CMOS relaxation oscillators,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 1375-1378. doi: 10.1109/ISCAS.2012.6271499

P. Shettigar and S.Pavan, “A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS,” 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2012, pp. 156-158. (Winner of the ISSCC 2012 Silk Road Award) doi: 10.1109/ISSCC.2012.6176957

R. Zanbaghi, S. Saxena, G. C. Temes and T. S. Fiez, “A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. doi: 10.1109/TCSI.2012.2206509

S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram and T. S. Fiez, “A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. doi: 10.1109/TCSI.2012.2206506

Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control,” 2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, 2012, pp. 182-183. doi: 10.1109/VLSIC.2012.6243850

Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts, “Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [Poster] poster

Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania and Debasish Behera, “A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay,” Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, San Jose, September 2011. doi: 10.1109/JSSC.2012.2196730

A. Jain, M. Venkatesan and S. Pavan, “A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range” 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, 2011, pp. 259-262. doi: 10.1109/ESSCIRC.2011.6044956

S. Thyagarajan, S. Pavan and P. Sankar, “Active-RC Filters Using the Gm-Assisted OTA-RC Technique,” IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1522-1533, July 2011. doi: 10.1109/JSSC.2011.2143590

Chembiyan Thambidurai and Nagendra Krishnapura, “On Pulse Position Modulation and Its Application to PLLs for Spur Reduction,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 7, pp. 1483-1496, July 2011. doi: 10.1109/TCSI.2011.2157749

S. Aniruddhan, Sudip Shekhar and David J. Allstot, “A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing”, IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 5, pp. 860-867, May 2011. doi: 10.1109/TCSI.2010.2090565

S. Pavan, “On Continuous-Time $\Delta\Sigma$ Modulators With Return-to-Open DACs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 5, pp. 284-288, May 2011. doi: 10.1109/TCSII.2011.2124930

Nagendra Krishnapura, Abhishek Agrawal and Sameer Singh, “A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 4, pp. 205-209, April 2011. doi: 10.1109/TCSII.2011.2124571

Nagendra Krishnapura, “Electronic time stretching for fast digitization,” 2011 IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, 2011, pp. 1391-1394. doi: 10.1109/ISCAS.2011.5937832

S. Pavan, “The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators”, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, 2011, pp. 526-529. doi: 10.1109/ISCAS.2011.5937618

A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'Shea, X. Quan, R. Rangarajan, J. Sankaranarayanan, A. See, R. Sridhara, B. Sun, W. Su, K. van Zalinge, G. Zhang and K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor,” 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011, pp. 368-370. doi: 10.1109/ISSCC.2011.5746357

S. Pavan, “Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 2, pp. 233-243, Feb. 2011. doi: 10.1109/TCSI.2010.2071930

R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW,” 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2011, pp. 1-4. doi: 10.1109/CICC.2011.6055287

S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer,” 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2011, pp. 1-4. doi: 10.1109/CICC.2011.6055290

S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,” IEEE Journal of Solid-State Circuits, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011. doi: 10.1109/JSSC.2011.2162921

Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang and P.K. Hanumolu, “A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control,” 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, 2011, pp. 439-442. doi: 10.1109/ESSCIRC.2011.6045001

S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre and P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,“ 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011, pp. 238-240. doi: 10.1109/ISSCC.2011.5746300

Janakiraman Viraraghavan, Bharadwaj Amrutur and V. Visvanathan, “Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 7, pp. 1056-1069, July 2010. doi: 10.1109/TCAD.2010.2049059

S. Pavan, “Design Techniques for High-Performance Continuous-time Delta Sigma Conversion,” half day tutorial at the European Solid State Circuits Conference, Seville, Spain, 2010.

S. Thyagarajan, S. Pavan and P. Sankar, “Low distortion active filters using the Gm-assisted OTA-RC technique,” 2010 Proceedings of ESSCIRC, Seville, 2010, pp. 162-165. doi: 10.1109/ESSCIRC.2010.5619904

V. Singh, N. Krishnapura and S. Pavan, “Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 676-680, Sept. 2010. doi: 10.1109/TCSII.2010.2058496

S. Pavan, “Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 1925-1934, Aug. 2010. doi: 10.1109/TCSI.2009.2039833

S. Pavan and P. Sankar, “Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique,” IEEE Journal of Solid-State Circuits, vol. 45, no. 7, pp. 1365-1379, July 2010. doi: 10.1109/JSSC.2010.2048082

N. Krishnapura, “Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, 2010, pp. 301-304. doi: 10.1109/ISCAS.2010.5537847

S. Parameswaran and N. Krishnapura, “A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, 2010, pp. 2410-2413. doi: 10.1109/ISCAS.2010.5537170

C. Thambidurai and N. Krishnapura, “Spur reduction in wideband PLLs by random positioning of charge pump current pulses,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, 2010, pp. 3397-3400. doi: 10.1109/ISCAS.2010.5537876

S. Pavan, “Understanding weak loop filter nonlinearities in continuous time ΔΣ converters,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, 2010, pp. 17-20. doi: 10.1109/ISCAS.2010.5537136

K. Reddy and S.Pavan, “A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range,” Analog Integr Circ Sig Process 63, 397–406 (2010) doi:10.1007/s10470-009-9413-8

S. Pavan, “Systematic Design Centering of Continuous Time Oversampling Converters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 3, pp. 158-162, March 2010. doi: 10.1109/TCSII.2010.2041814

S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan and P.K. Hanumolu, “A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction,” IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, 2010, pp. 1-4. doi: 10.1109/CICC.2010.5617443

K. Jayaraman, Q. Khan, B. Chi, W. Beattie, Z. Wang and P. Chiang, “A self-healing 2.4GHz LNA with on-chip S11/S21 measurement/calibration for in-situ PVT compensation,” 2010 IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA, 2010, pp. 311-314. doi: 10.1109/RFIC.2010.5477307

S.Pavan and P.Sankar, “A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range,” 2009 Proceedings of ESSCIRC, Athens, 2009, pp. 320-323. doi: 10.1109/ESSCIRC.2009.5325953

Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, “A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain,” 2009 IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, 2009, pp. 261-264. doi: 10.1109/ISCAS.2009.5117735

S.Saxena,P.Sankar and S.Pavan, “Automatic tuning of time constants in single bit continuous-time delta-sigma modulators,” 2009 IEEE International Symposium on Circuits and Systems, Taipei, 2009, pp. 2257-2260. doi: 10.1109/ISCAS.2009.5118248

N.Krishnapura, V.Gupta and N.Agrawal, “Compact lowpass ladder filters using tapped coils,” 2009 IEEE International Symposium on Circuits and Systems, Taipei, 2009, pp. 53-56.) doi: 10.1109/ISCAS.2009.5117683

V. Vasudevan, “Analysis of clock jitter in continuous-time quadrature bandpass sigma-delta modulators with NRZ pulses,” 2009 Ph.D. Research in Microelectronics and Electronics, Cork, 2009, pp. 176-179. doi: 10.1109/RME.2009.5201334

T.Laxminidhi, V.Prasadu and S.Pavan, “Widely Programmable High-Frequency Active RC Filters in CMOS Technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 2, pp. 327-336, Feb. 2009.. doi: 10.1109/TCSI.2008.2001759

L.Manojkumar, A.Mohan and N.Krishnapura, “A Comparison of Approaches to Carrier Generation for Zigbee Transceivers,” 2009 22nd International Conference on VLSI Design, New Delhi, 2009, pp. 367-372. doi: 10.1109/VLSI.Design.2009.50

N.Krishnapura and S.Pavan, “Negative Feedback System and Circuit Design,” 2009 22nd International Conference on VLSI Design, New Delhi, 2009, pp. 35-36. doi: 10.1109/VLSI.Design.2009.116

Janakiraman Viraraghavan, Bharadwaj Amrutur and V. Visvanathan, “Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks,” Journal of Low Power Electronics, Volume 4, Number 3, December 2008, pp. 301-319(19) doi:10.1166/jolpe.2008.187

Janakiraman Viraraghavan, Bishnu Prasad Das and Bharadwaj Amrutur, “Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization,” 21st International Conference on VLSI Design (VLSID 2008), Hyderabad, 2008, pp. 667-672. doi: 10.1109/VLSI.2008.38

Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni and N. V. Arvind, “Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations,” 21st International Conference on VLSI Design (VLSID 2008), Hyderabad, 2008, pp. 685-691. doi: 10.1109/VLSI.2008.92

V.Hareesh, S.Pavan and E.Bhattacharya, “Readout circuit design for an EISCAP biosensor,” 2008 IEEE Biomedical Circuits and Systems Conference, Baltimore, MD, 2008, pp. 73-76. doi: 10.1109/BIOCAS.2008.4696877

S.Pavan, “Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 11, pp. 1119-1123, Nov. 2008. doi: 10.1109/TCSII.2008.2008051

K. Reddy and S.Pavan, “A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range,” ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, 2008, pp. 210-213. doi: 10.1109/ESSCIRC.2008.4681829

S. Pavan, “Power and area-efficient adaptive equalization at microwave frequencies,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1412-1420, July 2008. doi: 10.1109/TCSI.2008.918149

Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan and David J. Allstot, “CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1177-1186, May 2008. doi: 10.1109/JSSC.2008.920360

S. Pavan, “Power and area efficient high speed analog adaptive equalization,” 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, 2008, pp. 3126-3129. doi: 10.1109/ISCAS.2008.4542120

K. Balemarthy and S. Pavan, “Signal Processing for Optical Fiber Communication”, Tutorial at the National Conference on Communication, February 1-3, Bombay, India. slides

S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, “A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 351-360, Feb. 2008. doi: 10.1109/JSSC.2007.914263

S. Pavan and N. Krishnapura, “Oversampling Analog-to-Digital Converter Design,” 21st International Conference on VLSI Design (VLSID 2008), Hyderabad, 2008, pp. 7-7. doi: 10.1109/VLSI.2008.130

A. Kokrady, C. P. Ravikumar and N. Chandrachoodan, “Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models,” 21st International Conference on VLSI Design (VLSID 2008), Hyderabad, 2008, pp. 169-174. doi: 10.1109/VLSI.2008.115

P. Sankar and S. Pavan, “Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 12, pp. 1125-1129, Dec. 2007. doi: 10.1109/TCSII.2007.905390

D.J. Allstot, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar and J.S. Walling, “Low phase noise CMOS voltage-controlled oscillators,” 2007 7th International Conference on ASIC, Guilin, 2007, pp. 297-302. doi: 10.1109/ICASIC.2007.4415626

K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. doi: 10.1109/TCSI.2007.905648

G. Kannan, N. Chandrachoodan and S. Srinivasan, “Rapid Abstract Control Model for Signal Processing Implementation,” 2007 IEEE Workshop on Signal Processing Systems, Shanghai, China, 2007, pp. 418-423. doi: 10.1109/SIPS.2007.4387584

T. Laxminidhi, V. Prasadu and S. Pavan, “A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS,” 2007 IEEE Custom Integrated Circuits Conference, San Jose, CA, 2007, pp. 683-686. doi: 10.1109/CICC.2007.4405824

S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, “A 90μW 15-bit ΔΣ ADC for digital audio,” ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, Munich, 2007, pp. 198-201. doi: 10.1109/ESSCIRC.2007.4430279

S. Pavan and T. Laxminidhi, “Accurate Characterization of Integrated Continuous-Time Filters,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. doi: 10.1109/JSSC.2007.900288

K. N. Parashar and N. Chandrachoodan, “A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation,” 2007 International Conference on Field Programmable Logic and Applications, Amsterdam, 2007, pp. 792-795. doi: 10.1109/FPL.2007.4380770

T. Laxminidhi and S. Pavan, “Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 7, pp. 1481-1488, July 2007. doi: 10.1109/TCSI.2007.899625

S. Shekhar, S. Aniruddhan, and D.J. Allstot, “A Tuned-Input Tuned-Output VCO in 0.18μm CMOS,” 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, HI, 2007, pp. 607-610. doi: 10.1109/RFIC.2007.380957

T. Laxminidhi and S. Pavan, “Accurate Characterization of Integrated Continuous-Time Filters,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1758-1766, Aug. 2007. doi: 10.1109/JSSC.2007.900288

S. Pavan, “Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization,” 2007 IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, 2007, pp. 3550-3553. doi: 10.1109/ISCAS.2007.378449

S. Pavan and N. Krishnapura, “Automatic Tuning of Time Constants in Continuous-Time Delta–Sigma Modulators,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 308-312, April 2007. doi: 10.1109/TCSII.2006.888920

S. Pavan and R. Tiruvuru, “Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 2, pp. 401-410, Feb. 2007. doi: 10.1109/TCSI.2006.887475

K.N.Vikram and V.Vasudevan, “Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 9, pp. 1010-1023, Sept. 2006. doi: 10.1109/TVLSI.2006.884052

V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, “A Distortion Compensating Flash Analog-to-Digital Conversion Technique,” IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 1959-1969, Sept. 2006. doi: 10.1109/JSSC.2006.880601

S. Pavan and T.Laxminidhi, “A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters,” IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, 2006, pp. 77-80. doi: 10.1109/CICC.2006.320980

S. Pavan and T.Laxminidhi, “A 70-500+MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects,” 2006 Proceedings of the 32nd European Solid-State Circuits Conference, Montreux, 2006, pp. 328-331. doi: 10.1109/ESSCIR.2006.307597

S. Murali and S. Pavan, “Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A,” IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, 2006, pp. 201-204. doi: 10.1109/CICC.2006.320910

Ponnmozhi S. and Nitin Chandrachoodan, “Design of Hardware Coprocessor for OTDR Application”, 11th IEEE VLSI Design and Test Symposium, VDAT 2006, Goa, India, August 2006.

S. Shekhar, S. Aniruddhan and D.J. Allstot, “A fully-differential CMOS Clapp VCO for IEEE 802.11a applications,” 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-. doi: 10.1109/ISCAS.2006.1693316

S. Aniruddhan, S. Shekhar and D.J. Allstot, “A delay generation technique for fast-locking frequency synthesizers,” 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-5466. doi: 10.1109/ISCAS.2006.1693870

A. Sharma and S. Pavan, “A single inductor multiple output converter with adaptive delta current mode control,” 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-. doi: 10.1109/ISCAS.2006.1693915

K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 10, pp. 2184-2194, Oct. 2007. doi: 10.1109/TCSI.2007.905648

T. Rajesh and S. Pavan, “Transmission line based FIR structures for high speed adaptive equalization,” 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-1054. doi: 10.1109/ISCAS.2006.1692769

K.N. Vikram and V. Vasudevan, “Scheduling divisible loads on partially reconfigurable hardware,” 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, 2006, pp. 289-290. doi: 10.1109/FCCM.2006.63

P. Rajesh Kumar, K. Sridharan and S. Srinivasan, “A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment,” Parallel Computing Journal, Elsevier, Vol. 32, No. 3, March 2006, pp. 205-221. doi: 10.1016/j.parco.2005.09.004

Kavish Seth, Viswajith, S. Srinivasan and V. Kamakoti, “Ultra folded high-speed architectures for Reed Solomon decoders,” 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Hyderabad, India, 2006, pp. 4 pp.-. doi: 10.1109/VLSID.2006.163

S. Pavan and S. Shivappa, “Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 1, pp. 177-192, Jan. 2006. doi: 10.1109/TCSI.2005.854610

S. Pavan, P. Easwaran and C. Srinivasan, “System aspects of analog to digital converter designs,” 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Hyderabad, India, 2006, pp. 1 pp.-. doi: 10.1109/VLSID.2006.154

Q. Khan and G. K. Siddhartha, “A sequence independent power-on-reset circuit for multi-voltage systems,” 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-. doi: 10.1109/ISCAS.2006.1692824

Q. Khan, G. K. Siddhartha, D. Tripathi, S. K. Wadhwa and K. Misri, “Techniques for on-chip process voltage and temperature detection and compensation,” 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Hyderabad, India, 2006, pp. 6 pp.-. doi: 10.1109/VLSID.2006.155

Q. Khan, S. K. Wadhwa and K. Misri, “A single supply level shifter for multi-voltage systems,” 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Hyderabad, India, 2006, pp. 4 pp.-. doi: 10.1109/VLSID.2006.24

K.N.Vikram and V.Vasudevan, “Hardware-software co-simulation of bus-based reconfigurable systems”, Microprocessors and Microsystems, vol. 29(4), pp 133-144, May 2005. doi: 10.1016/j.micpro.2004.07.004

K.P.Sunil Rafeeque and V.Vasudevan, ” A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters,“ IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2348-2357, Nov. 2005. doi: 10.1109/TCSI.2005.853587

N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar and A. Aggarwal, “A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission,” ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., San Francisco, CA, 2005, pp. 60-585 Vol. 1. doi: 10.1109/ISSCC.2005.1493868

S. Pavan and S. Shivappa, “Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers,” 2005 IEEE International Symposium on Circuits and Systems, Kobe, 2005, pp. 5962-5965 Vol. 6. doi: 10.1109/ISCAS.2005.1465997

S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau, “Design considerations for Integrated Modulator Drivers in SiGe Technology,” International Journal of High Speed Electronics and Systems, Vol. 15, No. 03, pp. 477-495 (2005). doi: 10.1142/S0129156405003284

D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, “Circuit techniques for CMOS multiple-antenna transceivers,” 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers, Long Beach, CA, USA, 2005, pp. 225-228. doi: 10.1109/RFIC.2005.1489639

D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,”Recent advances and design trends in CMOS radio frequency integrated Circuits“, International Journal of High Speed Electronics and Systems, vol.15, no.2, pp 377-428, June 2005. doi: 10.1142/9789812774583_0006

V.Vasudevan, “Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits,” Proceedings. 42nd Design Automation Conference, 2005., Anaheim, CA, 2005, pp. 397-402. doi: 10.1145/1065579.1065685

S. Aniruddhan and D.J. Allstot, “Architectural issues in base-station frequency synthesizers,” 2005 IEEE International Symposium on Circuits and Systems, Kobe, 2005, pp. 6034-6037 Vol. 6. doi: 10.1109/ISCAS.2005.1466015

S. Ramachandran and S. Srinivasan, “Design and FPGA Implementation of an MPEG based Video Scalar with reduced on-chip memory utilization”, Journal of Systems Architecture, Elsevier Publications, Vol. 51, pp. 435-450, 2005. doi: 10.1016/j.sysarc.2004.07.008

K.N. Vikram, V. Vasudevan and S.Srinivasan, “Rate-distortion estimation for fast JPEG2000 compression at low bit-rates,” Electronics Letters, vol. 41, no. 1, pp. 16-18, 6 Jan. 2005. doi: 10.1049/el:20057147

S.Singh and S.Srinivasan, “Architecturally efficient FFT pruning algorithm,” Electronics Letters, vol. 41, no. 23, pp. 1305-1306, 10 Nov. 2005. doi: 10.1049/el:20052994

P.Rajesh Kumar, K.Sridharan and S.Srinivasan, “An efficient algorithm for topological map construction in a planar environment explored using proximity sensors,” Proceedings of 2005 International Conference on Intelligent Sensing and Information Processing, 2005., Chennai, India, 2005, pp. 67-72. doi: 10.1109/ICISIP.2005.1529422

K.P. Sunil Rafeeque and V.Vasudevan, “A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs”, Journal of Electronic Testing:Theory and Applications, vol. 20, pp 623-638, Dec. 2004. doi: 10.1007/s10677-004-4250-4

K.P.S.Rafeeque and V.Vasudevan, “A built-in-self-test scheme for digital to analog converters,” 17th International Conference on VLSI Design. Proceedings., Mumbai, India, 2004, pp. 1027-1032. doi: 10.1109/ICVD.2004.1261065

K.P.Sunil Rafeeque and V.Vasudevan, “An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, 2004, pp. I-I. doi: 10.1109/ISCAS.2004.1328186

N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “The hierarchical timing pair model for multirate DSP applications,” IEEE Transactions on Signal Processing, vol. 52, no. 5, pp. 1209-1217, May 2004. doi: 10.1109/TSP.2004.826178

S. Aniruddhan, M.Chu and D.J. Allstot, “A lateral-BJT-biased CMOS voltage-controlled oscillator,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, 2004, pp. I-976. doi: 10.1109/ISCAS.2004.1328360

S. Pavan, “A fixed transconductance bias technique for CMOS analog integrated circuits,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, 2004, pp. I-661. doi: 10.1109/ISCAS.2004.1328281

S. Pavan, “Continuous-time integrated FIR filters at microwave frequencies,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 1, pp. 15-20, Jan. 2004. doi: 10.1109/TCSII.2003.821522

V.Vasudevan, “A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 422-433, Feb. 2004. doi: 10.1109/TCSI.2003.822553

V.Vasudevan, “A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 11, pp. 2175-2178, Nov. 2004. doi: 10.1109/TCSI.2004.836858

V.Vasudevan and M.Ramakrishna “Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 11, pp. 2165-2174, Nov. 2004. doi: 10.1109/TCSI.2004.836844

Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti and V. Bala Kuteshwar, “A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation,” 17th International Conference on VLSI Design. Proceedings., Mumbai, India, 2004, pp. 1071-1076. doi: 10.1109/ICVD.2004.1261071

Q. Khan, S. K. Wadhwa and K. Misri, “A tunable g/sub m/-C filter with low variation across process, voltage and temperature,” 17th International Conference on VLSI Design. Proceedings., Mumbai, India, 2004, pp. 539-544. doi: 10.1109/ICVD.2004.1260975

N. Krishnapura and Y. Tsividis, “Micropower low-voltage analog filter in a digital CMOS process,” IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 1063-1067, June 2003. doi: 10.1109/JSSC.2003.811986

S. Kudszus, A. Shahani, S.Pavan, D. Schaffer and M. Tarsia, “A 46-GHz distributed transimpedance amplifier using SiGe bipolar technology,” IEEE MTT-S International Microwave Symposium Digest, 2003, Philadelphia, PA, USA, 2003, pp. 1387-1390 vol.2. doi: 10.1109/MWSYM.2003.1212630

S. Pavan, ” Analog FIR Filters at Microwave Frequencies,“ Proceedings of the National Conference on Communications, IIT Madras, Chennai, February 2003. paper

V.Vasudevan and M.Ramakrishna, “Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique,” Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), Anaheim, CA, 2003, pp. 538-541. doi: 10.1145/775832.775968

V.Vasudevan, “A time-domain technique for computation of noise spectral density in switched capacitor circuits,” Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., Bangkok, 2003, pp. I-I.. doi: 10.1109/ISCAS.2003.1205631

Y. Tsividis, N. Krishnapura, Y. Palaskas and L. Toth, “Internally varying analog circuits minimize power dissipation,” IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 63-72, Jan. 2003. doi: 10.1109/MCD.2003.1175109

Srikar Movva and S. Srinivasan, “A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation,” 16th International Conference on VLSI Design, 2003. Proceedings., New Delhi, India, 2003, pp. 202-207. doi: 10.1109/ICVD.2003.1183137

K. Gupta and S. Srinivasan, “Reduced memory implementation of modified serial watershed algorithm based on ordered queue,” Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing, Las Vegas, NV, USA, 2003, pp. 514-518. doi: 10.1109/ITCC.2003.1197582

A. Kishore and S. Srinivasan, “A distributed memory architecture for morphological image processing,” Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing, Las Vegas, NV, USA, 2003, pp. 536-540. doi: 10.1109/ITCC.2003.1197586

S. Ramachandran and S. Srinivasan, “Design and FPGA implementation of a video scalar with on-chip reduced memory utilization,” Euromicro Symposium on Digital System Design, 2003. Proceedings., Belek-Antalya, Turkey, 2003, pp. 206-213. doi: 10.1109/DSD.2003.1231927

P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan, “A pipelined cellular architecture for Euclidean distance transform,” TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region, Bangalore, India, 2003, pp. 1153-1156 Vol.3. doi: 10.1109/TENCON.2003.1273428

Q. Khan and D. Dutta, “A programmable CMOS bandgap voltage reference circuit using current conveyor,” 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, Sharjah, 2003, pp. 8-11 Vol.1. doi: 10.1109/ICECS.2003.1301963

Q. Khan, S. Wadhwa and K. Misri, “Low power startup circuits for voltage and current reference with zero steady state current,” Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03., Seoul, South Korea, 2003, pp. 184-188. doi: 10.1109/LPE.2003.1231859

Q. Khan, S. Wadhwa and K. Misri, “A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature,” 16th International Conference on VLSI Design, 2003. Proceedings., New Delhi, India, 2003, pp. 504-506. doi: 10.1109/ICVD.2003.1183184

N. Chandrachoodan, “Performance Analysis and Hierarchical Timing for DSP System Synthesis”, PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, August 2002. Paper

N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “High-level synthesis of DSP applications using adaptive negative cycle detection.”, EURASIP Journal on Applied Signal Processing, 2002(9):893-907, September 2002. doi: 10.1155/S1110865702205053

S.Ramachandran and S.Srinivasan, “A fast FPGA-based MPEG-2 image encoder with a novel automatic quality control scheme” Elsevier Science, Microprocessors and Microsystems, Vol.25, pp. 449-457, 2002 doi: 10.1016/S0141-9331(01)00138-7

S. Ramachandran and S. Srinivasan, “A novel automatic quality control scheme for real time image transmission,” VLSI Design Journal, USA, Vol. 14(4), pp. 329-335, 2002. doi: 10.1080/10655140290011131

S. Ramachandran and S. Srinivasan, “A dynamically reconfigurable video compression scheme using FPGAs with coarse-grain parallelism”, VLSI Design Journal, USA Vol. 15(2), pp. 521-528, 2002. doi: 10.1080/1065514021000012138

K. Seth and S. Srinivasan, “Data scheduling scheme for power reduction in DWT-based image coders,” Electronics Letters, vol. 38, no. 9, pp. 408-409, 25 April 2002. doi: 10.1049/el:20020291

Kavish Seth and S.Srinivasan, “VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme,” Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, Bangalore, India, 2002, pp. 435-440. doi: 10.1109/ASPDAC.2002.994959

D. Frey, Y. Tsividis, G. Efthivoulidis and N. Krishnapura, “Syllabic-companding log domain filters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 4, pp. 329-339, April 2001. doi: 10.1109/82.933791

G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, “A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation,” Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), San Diego, CA, 2001, pp. 153-156. doi: 10.1109/CICC.2001.929745

N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “Adaptive negative cycle detection in dynamic graphs,” ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), Sydney, NSW, 2001, pp. 163-166 vol. 5. doi: 10.1109/ISCAS.2001.922010

N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “An efficient timing model for hardware implementation of multirate dataflow graphs,” 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), Salt Lake City, UT, USA, 2001, pp. 1153-1156 vol.2. doi: 10.1109/ICASSP.2001.941126

N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “The hierarchical timing pair model.”, Proceedings of the International Symposium on Circuits and Systems, pages V-367-V-370, Sydney, Australia, May 2001. doi:10.1109/ISCAS.2001.922061

N. Krishnapura and Y. Tsividis, “A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process,” 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), Kyoto, Japan, 2001, pp. 179-182. doi: 10.1109/VLSIC.2001.934231

N. Krishnapura and Y. Tsividis, “Dynamically biased 1 MHz low-pass filter with 61 dB peak SNR and 112 dB input range,” 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), San Francisco, CA, USA, 2001, pp. 360-361. doi: 10.1109/ISSCC.2001.912673

N. Krishnapura and Y. Tsividis, “Noise and power reduction in filters through the use of adjustable biasing,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. doi: 10.1109/4.972141

S.Ramachandran and S.Srinivasan, “FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression,” Ninth International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, Feb., 2001. doi: 10.1145/360276.360358

K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process”, IEEE Journal of Solid State Circuits, December 2000. doi:10.1007/978-1-4757-3198-9_2

K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A 700M Sample/s 6 b read channel A/D converter with 7 b servo mode,” 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), San Francisco, CA, USA, 2000, pp. 426-427. doi: 10.1109/ISSCC.2000.839844

K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS”, Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000. doi:10.1007/978-1-4757-3198-9_2

N. Krishnapura and P. Kinget, “A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1019-1024, July 2000. doi: 10.1109/4.848211

N. Krishnapura, Y. Tsividis and D. R. Frey, “Simplified technique for syllabic companding in log-domain filters,” Electronics Letters, vol. 36, no. 15, pp. 1257-1259, 20 July 2000. doi: 10.1049/el:20000978

S. Pavan and Y. Tsividis, “Time-scaled electrical networks. Properties and applications in the design of programmable analog filters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 161-165, Feb. 2000. doi: 10.1109/82.823547

S. Pavan, Y. Tsividis and K. Nagaraj, “Widely programmable high-frequency continuous-time filters in digital CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 503-511, April 2000. doi: 10.1109/4.839910

Shrenik Patel and S.Srinivasan, ““Modified embedded zerotree wavelet algorithm for fast implementation of wavelet image codec,” Electronics Letters, vol. 36, no. 20, pp. 1713-1714, 28 Sept. 2000. doi: 10.1049/el:20001212

S.Ramachandran and S.Srinivasan, “A programmable pruning level control based MPEG video encoder,” 2000 IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, 2000, pp. 571-574 vol.1. doi: 10.1109/ISCAS.2000.857159

S.Ramachandran and S.Srinivasan, “Design and implementation of an EPLD-based variable length coder for real time image compression applications,” 2000 IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, 2000, pp. 607-610 vol.1. doi: 10.1109/ISCAS.2000.857168

N. Krishnapura and P. Kinget, “A 5.3GHz programmable divider for HiPerLAN in 0.25 µm CMOS,” Proceedings of the 25th European Solid-State Circuits Conference, Duisburg, Germany, 1999, pp. 142-145. Paper

S. Pavan, Y. Tsividis and K. Nagaraj, “A 60-350 MHz programmable analog filter in a digital CMOS process,” Proceedings of the 25th European Solid-State Circuits Conference, Duisburg, Germany, 1999, pp. 46-49. Paper

S. Pavan, Y. Tsividis and K. Nagaraj, “Modeling of accumulation MOS capacitors for analog design in digital VLSI processes,” 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, 1999, pp. 202-205 vol.6. doi: 10.1109/ISCAS.1999.780130

D.V.R. Murthy, S. Ramachandran and S. Srinivasan, “Parallel implementation of 2D-discrete cosine transform using EPLDs,” Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), Goa, India, 1999, pp. 336-339. doi: 10.1109/ICVD.1999.745178

S.Ramachandran, S.Srinivasan and R.Chen, “EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression,” 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, 1999, pp. 375-378 vol.3. doi: 10.1109/ISCAS.1999.778863

T.G.Venkatesh and S.Srinivasan, “A pruning based fast rate control algorithm for MPEG coding,” Proceedings Third International Conference on Computational Intelligence and Multimedia Applications. ICCIMA'99 (Cat. No.PR00300), New Delhi, India, 1999, pp. 403-407. doi: 10.1109/ICCIMA.1999.798564

L. Toth, Y. Tsividis and N. Krishnapura, “Analysis of noise and interference in companding signal processors,” 1998 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, 1998, pp. 143-146 vol.1. doi: 10.1109/ISCAS.1998.704209

L. Toth, Y. Tsividis and N. Krishnapura, “On the analysis of noise and interference in instantaneously companding signal processors,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 9, pp. 1242-1249, Sept. 1998. doi: 10.1109/82.718591

N. Krishnapura, S. Pavan, C. Mathiazhagan and B. Ramamurthi, “A baseband pulse shaping filter for Gaussian minimum shift keying,” 1998 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, 1998, pp. 249-252 vol.1. doi: 10.1109/ISCAS.1998.704333

N. Krishnapura, Y. Tsividis, K. Nagaraj and K. Suyama, “Companding switched capacitor filters,” ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), Monterey, CA, 1998, pp. 480-483 vol.1. doi: 10.1109/ISCAS.1998.704507

S. Pavan and Y. Tsividis, “An analytical solution for a class of oscillators, and its application to filter tuning,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no. 5, pp. 547-556, May 1998. doi: 10.1109/81.668866

S. Pavan and Y. Tsividis, “An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning”, IEEE Transactions on Circuits and Systems-I, vol. 45, no. 9, pp. 1242-1249, May 1998. doi: 10.1109/81.668866

S. Venkatesh and S. Srinvasan, “Modified butterfly structure for efficient implementation of pruned fast cosine transform,” Electronics Letters, vol. 34, no. 14, pp. 1383-1385, 9 July 1998. doi: 10.1049/el:19980977

S. Srinivasan and B. Srikanth, “Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, International Conference on Computational Intelligence and Multimedia Applications, Churchill, Australia, Feb 1998.

S. Venkatesh, S. Srinivasan and R.Chen, “An efficient implementation of a progressive image transmission system using successive pruning algorithm on a parallel architecture,” Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238), Madras, India, 1998, pp. 445-451. doi: 10.1109/HIPC.1998.738020

P. Yadav and S. Ramprasath, ” Keep-through regions for handling end-of-line rules in routing,” US 11,586,796 B1, Feb. 21, 2023. US11586796B1

M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, “Current measurments in switching regulators”, US 9,755,518, September 5, 2017. US9755518B2

M. Bansal, Q. Khan and C. Shi, “Average current mode control of multi-phase switching power converters,” US 9,442,140, Sep. 13, 2016. JP6185194B2

Qadeer A. Khan,Sandeep Chaman Dhar,Joshua A. ZAZZERA,Todd R. Sutton, “Circuits and Methods for Driving Resonant Actuators,” US 9,344,022, May 17, 2016. WO2015038703A1

Davinder Aggarwal, Vibhor Jain and Janakiraman VIRARAGHAVAN, “Automated design rule checking (DRC) test case generation,” US 8,875,064, Oct 28, 2014. US8875064B2

Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh and Janakiraman VIRARAGHAVAN, “Generic design rule checking (DRC) test case extraction”, US 9,292,652, Mar 22 2016. US9292652B2

C. Narathong and S. Aniruddhan, “Multi-mode Configurable Transmitter Circuit”, US 8,099,127, Jan. 17, 2012. US8099127B2

C. Narathong, S. Aniruddhan and W. Su, “Amplifier with Gain Expansion Stage”, US 8,035,443, Oct. 11, 2011. US8035443B2

B. Sun, S. Aniruddhan and S. Sridhara, “Method and Apparatus for Divider Unit Synchronization”, US 7,965,111, Jun. 25, 2011. US7965111B2

S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, “Mixer with High Output Power Accuracy and Low Local Oscillator Leakage”, US 7,941,115, May 10, 2011. US7941115B2

C. Narathong and S. Aniruddhan, “Techniques for improving Balun Loaded-Q”, US 7,863,986, Jan. 4, 2011. US20100033253A1

Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha and K. Misri, “PVT Variation Detection and Compensation Circuit”, US 7495465, Feb. 24, 2009. US7495465B2

D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri and S. Wadhwa, “PVT Variation Detection and Compensation Circuit”, US 7446592, Nov. 4, 2008. US7446592B2

Q. Khan and G.K. Sidhartha, “Sequence-independent Power-on Reset for Multi-Voltage Circuits”, US 7432748, Oct. 7, 2008. US7432748B2

D. Tripathi, J. Banerjee and Q. Khan, “Differential Receiver Circuit”, US 7414462, Aug. 19, 2008. US7414462B2

Q. Khan, H. Fukazawa and T. Nandurkar, “Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit”, US 7388422, Jun. 17, 2008. US7388422B2

G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa and K. Misri, “PVT Variation Detection and Compensation Circuit”, US 7388419, Jun. 17, 2008. US7388419B2

Isaac Shpantzer, Michael Tseytlin, Yaakov Achiam, Aviv Salamon, Israel Smilanski, Olga Ritterbush, Pak Shing Cho, Li Guoliang, Jacob Khurgin, Yehouda Meiman, Alper Demir, Peter Feldman, Peter Kinget, Nagendra Krishnapura, Jaijeet Roychowdhury, Joseph Schwarzwalder and Charles Sciabarra, “System and method for code division multiplexed optical communication”, US 7,167,651, Jan. 23, 2007. US7167651B2

Q. Khan and D. Tripathi, “Transmission Line Driver Circuit”, US 7292073, Nov. 6, 2007. US7292073B2

D. Tripathi, Q. Khan and K. Misri, “Transmission Line Driver”, US 7187197, Mar. 6, 2007. US7187197B2

S. Wadhwa, Q. Khan, K. Misri and D. Muhury, “Digital Clock Frequency Doubler”, US 7132863, Nov. 7, 2006. US7132863B2

Q. Khan, D. Tripathi and K. Misri, “High Voltage Level Converter Using Low Voltage Devices”, US 7102410, Sep. 5, 2006. US7102410B2

Q. Khan, S. Wadhwa and K. Misri, “Bandgap Reference Circuit,” US 7084698, Aug. 1, 2006. US7084698B2

Q. Khan, S. Wadhwa and K. Misri, “Bidirectional Level Shifter”, US 7061299, Jun, 13, 2006. US7061299B2

Q. Khan, S. Wadhwa and K. Misri, “Single Supply Level Shifter”, US 7009424, Mar. 7, 2006. US7009424B2

Shanthi Pavan, “Integrated circuit implementation for power and area efficient adaptive equalization”, US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California. US7142596B2

Isaac Shpantzer, Yehouda Meiman, Michael Tseytlin, Olga Ritterbush, Aviv Salamon, Peter Feldman,Alper Demir,Peter Kinget, Nagendra Krishnapura and Jaijeet Roychowdhury, “System and method for orthogonal frequency division multiplexed optical communication”, US 7,076,169, Jul. 11, 2006. US7076169B2

John S. Wang, Sudeep Bhoja, Shanthi Pavan and Hai Tao, “Method and apparatus for improved high-speed adaptive equalization”, US 7,003,228, Feb. 21, 2006. US7003228B2

George Palaskas and Shanthi Y. Pavan, “Mobility Compensation in MOS Integrated Circuits”, US 6,822,505, 23 Nov. 2004. US6822505B1

N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,816,003, Nov. 9, 2004. US6816003B2

N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,717,461, Apr. 6, 2004. US6717461B2

N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,683,492, Jan. 27, 2004. US6683492B2

P. Kinget and N. Krishnapura, “Glitch Free Phase Switching Synthesizer”, US 6,671,341, Dec. 30, 2003. US6671341B1

Shanthi Pavan and Arvin Shahani, “Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier”, US 6,552,615, 22 Apr. 2003. US6552615B1

Shanthi Pavan, Sudeep Bhoja and John S. Wang, “Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells”, US 6,545,567, 8 Apr. 2003. US6545567B1

Shanthi Pavan, “Fixed Transconductance Bias Apparatus”, US 6,400,185, 4 Jun. 2002. US6400185B2

Krishnaswamy Nagaraj and Shanthi Y. Pavan, “Fast Acting Polarity Detector”, US 6,369,726, 2 Apr. 2002. US6369726B1

Shanthi Pavan, “Low Distortion Sample-and-Hold Circuit”, US 6,323,697, 27 Nov. 2001. US6323697B1

Shanthi Pavan, “High Frequency Boost Technique”, US 6,304,134, 16 Oct. 2001. US6304134B1

P. Kinget and N. Krishnapura, “Programmable Frequency Divider”, US 6,281,721, Aug. 28, 2001. US6281721B1

Yendluri Shanthi-Pavan, Krishnaswamy Nagaraj and Venugopal Gopinathan, “Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation”, US 5,945,889, 31 Aug. 1999. US5945889A