A dynamically reconfigurable video encoder to switch among many different applications is designed. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG-1, MPEG-2, and H.263 standards. The scheme has emerged as an efficient and cost-effective solution for video compression as a result of innovative design using well-partitioned algorithms, highly pipelined architecture and coarse-grain parallelism. The reconfiguration time of the video encoder is less than 320 microseconds while switching from one standard to another. Although the dynamic reconfiguration scheme is presented for a video encoder, the same design methodology may be applied effectively for any other application.
The design incorporates several novel ideas and algorithms such as controlling image quality on the fly. As a result of this new feature, which uses a concept called pruning, the processing speed increases by a factor of two when compared to the conventional method of processing without pruning. The design also integrates a new, fast, one step search algorithm for motion estimation in video frame sequences along with automatic assessment of direction of motion of image blocks. The design has been realized by using HDL codes, schematic entries and parameterized modules with a chip set complexity of about 3,50,000 logic gates. The FPGA implementation conforms to JPEG to MPEG-2 standards and is capable of processing color pictures of sizes of up to 1024 x 768 pixels at the real time rate of 25 frames/second.