The project is a hardware implementation for obtaining compressed, good quality image capture of the GSLV/PSLV launch vehicle, especially during stage separation. This requires high performance hardware such as FPGA or ASIC to cope with the requirements of high speed, moderate compression and good quality. Hence, FPGA based implementation of the video codec (encoder/decoder) has been undertaken. At the encoder end, data acquired from a camera is passed onto an interface module which brings about format change from raster scan order to block format and stored in a pair of on-chip, dual-redundant memories. After preprocessing the stored original image, discrete wavelet and quantization (DWTQ) is computed. The ensuing coefficients are stored in on-chip, dual-redundant memories and bit plane coding (BPC) is applied, which organizes the data into a form suitable for efficient arithmetic coding (BAC). The bit stream is organized as header information followed by compressed image data and is transmitted over a serial radio link from the launch vehicle in flight. At the ground control, decoder hardware reconstructs the compressed image received from the launch vehicle.