Integrated Circuits and Systems group, IIT Madras

Parallel Implementation of JPEG Compression using Dual Processors.

By N.L. Vishvanathan

Abstract

The objective of this work is to develop a parallel processing system for JPEG compression of continuous-tone still images. The system is based on a DSP processor and a PC-AT. The compression algorithm is split into two independent assignments having approximately the same computational complxity and then allocated to the DSP and the host processor based on their individual merits with reference to the computed tasks. One of the two general purpose external flags of the DSP is used to facilitate interprocessor data transfers and communications. As the assignments are independent, they are computed concurrently on the two processors and this results in a twofold increase in the computational speed. As the compression algorithm is data driven, a provision has been made to adjust the algorithm, which will enable the user to obtain higher accuracy in exchange for less effective compression. In addition, as a part of this work, a comparitive study of the performance of two DSP processors viz.,the Texas Instruments' TMS320C30 and the Motorola's DSP56001, for this application has been carried out. Further more, a DSP56001 based PC add-on card has also been designed for this and similar applications.