By Srikar Movva

Keywords: Wavelet Transform, JPEG2000, Convolution-based, Lifting-based, Single Sample Overlap scheme, Non-expansive Symmetric Extension scheme

Everyday, an enormous amount of information is stored, processed and transmitted digitally. Much of this information is graphical or pictorial in nature and hence the storage and communications requirements are immense. Methods of compressing the data prior to storage and transmission are of significant practical and commercial interest. Image compression addresses the problem of reducing the amount of data required to represent a digital image. With the increasing use of multimedia technologies, image compression requires high performance as well as new features. To address these needs in the specific area of still image encoding, a new standard has been developed by Joint Photographic Experts Group (JPEG) known as JPEG2000. The standard supports two filtering modes: a convolution-based and a lifting-based. The lifting-based scheme is new compared to the convolution-based scheme. Extension schemes are used in image compression to reduce blocking artifacts. Single Sample Overlap (SSO) scheme is used in conjunction with the lifting-based algorithms and Non-expansive Symmetric Extension (NSE) scheme is used in conjunction with the convolution-based algorithms.

In this work, the performance of Two-Dimensional (2-D) lifting-based Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) with the SSO scheme is compared with 2-D convolution-based DWT and IDWT with the NSE scheme based on software implementations. Lifting-based 2-D DWT and IDWT algorithms with the SSO scheme are implemented in hardware. Algorithmic strength reduction techniques are applied to lifting-based 2-D DWT and IDWT algorithms with the SSO scheme to reduce their computational complexities. Architectural optimization techniques are applied to implement these reduced complexity algorithms. Based on these optimizations, novel architectures are proposed for the lifting-based 2-D DWT and IDWT algorithms with the SSO scheme. The functionality of these architectures is verified by laying them on silicon using 0.35 mm, 3.3 V, 3-Metal and 2-Poly CMOS technology.