By R.Krishnan

Hardwired implementation of digital filters are preferred for high sampling rate applications. Digital filters are pipelined to achieve high sampling rates. FIR filters can be pipelined in a fairly straight forward manner. However, IIR filters are pipelined by the “loop unfolding” technique which calls for larger silicon area. This thesis is an attempt to tackle this problem.

To overcome the above problem, a novel method to implement high sample rate IIR filters is presented. This uses resource sharing and pipelining to minimize the area-delay product. An FIR filter is “overlapped” over the hardware units of the IIR loop, trading off speed for silicon area. The validity, feasibility and usefulness of the technique are demonstrated. CAD tools have been used for verification and analysis.

Standard-Cell based architectures for a first order IIR filter are implemented and their performance analyzed using CAD tools. A clocking speed of 133 MHz at 0.44um CMOS technology at a power dissipation of 424 mw is achieved.