By Sanjeev Dua

This work is on the problem of onboard processing for satellite data communication, specifically, on the development of modem algorithms and their implementation by proper partitioning of the computational load between DSP and FPGA.

In the first part of the work, we design carrier offset estimation and timing recovery algorithms that work assuming a known training sequence. We evaluate their performance by comparing the BER curves of an ideal system with the one having carrier and timing offsets.

In the second part, these algorithms are optimized from a computational point of view. We examine them closely, to identify the parts that might prove to be bottlenecks in achieving higher data rates. Parts exhibiting bit level parallelism are identified, so that processing time can be reduced by designing new high speed hardware architectures and implementing them on FPGA. A new DA-OBC based, reduced ROM size, architecture for sampling rate converter is designed. A ROM-less digital frequency synthesizer with approximately 60 dB spurious frequency rejection is also presented.