Integrated Circuits and Systems group, IIT Madras

Integrated Circuits and Systems group, IIT Madras

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PUBLICATIONS IN CONFERENCE PROCEEDINGS

  1. S. Srinivasan and P.C. Rai, “A Follow-the-master Bandpass Filter Using CMOS Arrays For Video Applications”, IETE (India) Conference on Circuits and Systems, Madras, 1980.
  2. J.R. Perinbam and Srinivasan, “A Novel Differential Phase Correction For NTSC Signal”, 13th International Television Symposium, Montreux, Switzerland, May 1983.
  3. P.M. Farralle, S. Srinivasan and A.K. Jain, “A Unified Transform architecture”, International Conference on Acoustics, Speech and Signal Processing, Tokyo, Mar. 1986.
  4. S. Srinivasan, A.K. Jain and T.M. Chin, “Cosine Transform Block CODEC For Images Using The TMS 32010”, International Conference On Circuits and Systems, San Jose, California, May 1986.
  5. S. Srinivasan, K. Palaniswami and A.E. Natarajan, “Machine Recognition Of Indian Language Characters Using A Tree Structure Based On Primitives”, International Symposium on Pattern Recognition , Paris, Oct. 1986.
  6. J.B. Van Tighem, A.K. Jain and S. Srinivasan, “Image Processing With DSP And SIMD Chips”, International Symposium of Signal Processing and Applications, Brisbane, Aug. 1987.
  7. G. Umamaheswari, S. Srinivasan and C. Eswaran, “DSP Architectures: Current Trends And Desirable Features”, Midwest Symposium on Circuits and Systems, Syracuse, New York, 1987.
  8. S. Srinivasan and H.J.Z.Xia, “Comparison of Two DSP Architectures For Implementation Of Image Processing Algorithms”, Midwest Symposium on Circuits and Systems, St, Louis Missouri, Aug. 1988.
  9. S. Srinivasan and T.Bui, “A DSP Add-on Board For The IBM PC Using The TMS 32020 ”, Midwest Symposium on Circuits and Systems, St. Louis, Missouri, Aug. 1988.
  10. S. Srinivasan and H. Govindaraj, “A Multi-processor System Design Using TMS 320C25 Fo Real-time Image Processing”, International Symposium on Circuits and systems, Portland, Oregon, May 1989.
  11. S. Srinivasan, A. Singh and S.S. Gill, “A Novel Addressing Scheme For Two Dimensional Data Access In Digital Signal Processors”, 23rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, Oct. - Nov. 1989.
  12. S. Srinivasan, Elwin Chandra Monie and G. Vijaya Krishna Prasad. “Design Of A Real-time Image Compression System Using Multiple DSP 56000/96000 Processors”, 27th Asilomer Conference on Signals, Systems and Computers, Asilomar, Calif., Nov.1-3, 1993.
  13. H.C. Nagaraj, S. Radhakrishnan and S. Srinivasan, “Acquisition And Analysis Of Brainstem Auditory Evoked Responses”, International Conference of Biomedical Engineering, Hyderabad, India, Jan. 6-8, 1994.
  14. Elwin Chandra Monie and S. Srinivasan, “Image Compression Scheme Based On Adaptive Resonance Theory Neural Network Architecture”, National Seminar on Modern Telecommunication Networks, Coimbatore, India, Oct. 1994.
  15. H.C. Nagaraj, S. Radhakrishnan and S. Srinivasan, “Real-time Recording System For Brainstem Auditory Evoked Responses And The Study Of Stimulus Polarity Effects”, IEEE Regional Conference on Biomedical Engineering, Delhi, India, Feb. 1995.
  16. Elwin Chandra Monie and S. Srinivasan, “Vector Quantization Of Color Images Using Adaptive Resonance Theory Neural Network”, Sixth International Symposium on IC Technology Systems and Applications , Singapore, Sept.1995.
  17. N.L. Vishvanathan and S. Srinivasan, “Efficient Implementation Of JPEG Compression Using Dual Processors”, Sixth International Symposium on IC Technology Systems and Applications, Singapore, Sept. 1995.
  18. Elwin Chandra Monie and S. Srinivasan, “Coding Of Image Sequences Using Adaptive Resonance Theory Neural Network”, IASTED International Conference on Signal and Image Processing, Las Vegas, USA, Nov.1995.
  19. G.V.K. Prasad, K.M. Patil, S. Srinivasan and P.K. Oomen, “Spectral Analysis Of EMG Signals Using TMS320C25 Processor”, Fifth National Conference of Biomechanics, Madras, Feb.1996.
  20. H.C. Nagaraj, S. Radhakrishnan, S. Srinivasan, S.S.K. Ayyar and M. Ramesh, “Spectral Analysis Of Brainstem Auditory Evoked Responses”, Fifth National Conference of Biomechanics, Madras, Feb.1996.
  21. R. Srivaths and S. Srinivasan, “ Content Based Image Retrieval”, International Conference on Multimedia Technology and Management, Hong Kong, Dec.11-14, 1996.
  22. Anand Rangarajan and S. Srinivasan “Personalised Trailer Making Of MPEG Sequences”, International Conference on Multimedia Technology and Management, Hong Kong, Dec.11-14, 1996.
  23. H.C. Nagaraj, S. Srinivasan and S. Radhakrishanan “Spectral Estimation Of Brainstem Auditory Evoked Responses By Autoregressive Modelling,” International Conference on Biomedical Engineering, Coimbatore, Dec 1996.
  24. S.R. Rangarajan and S. Srinivasan “Fast Progressing Image Transmission By Successive Pruning”, National Conference on Communications, NCC, Madras, Jan-Feb 1997.
  25. V. Shankar, S. Srinivasan and S.R. Rangarajan, “Efficient Implementation Of MPEG Video Codec Using Dual Processors”, 13th International Conference on Digital Signal Processing , Sanforini, Greece, July 1997.
  26. S.R. Rangarajan and S. Srinivasan, “Fast Image Compression By Adaptive Pruning”, Conference on Signal Processing, Communication and Networking, Bangalore, July 1997.
  27. R. Krishnan and S. Srinivasan, “An Area Minimization Technique For Implementing Pipelined IIR Filters”, International Symposium on IC Technology, Systems and Application, ISIC-97, Singapore, Sep 1997.
  28. S. Srinivasan and B. Srikanth, “Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, International Conference on Computational Intelligence and Multimedia Applications, Churchill, Australia, Feb 1998.
  29. S. Venkatesh, S. Srinivasan and R.Chen. “An Efficient Implementation Of A Progressive Image Transmission System Using Successive Pruning Algorithm On A Parallel Architecture”, Intl. Conf. On High Performance Computing, Madras, India, Dec 1998.
  30. D.V.R. Murthy, S. Ramachandran and S. Srinivasan, ” Parallel Implementation Of 2D-Discrete Cosine Transform Using ELPDs“, Twelfth International Conference on VLSI Design, Goa, Jan 1999.
  31. S.Ramachandran, S.Srinivasan and R.Chen, “EPLD-based Architecture of Real Time 2D-Discrete Cosine Transform and quantization for Image Compression”, International Symposium on Circuits and Systems (ISCAS '99), Orlando, Florida, May - June 1999.
  32. T.G.Venkatesh and S.Srinivasan, “A Pruning based fast rate control algorithm for MPEG coding”, Third International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'99), New Delhi, Aug. 1999.
  33. K. Gopalakrishna Prabhu, K.Mothiram Patil, S.Srinivasan, V.B.Narayanamurthy and S.Parivalavan, “Early detection of neuropathy in diabetic feet by processing of pedobarographic images”, International Conference on Medical Diagnostic Techniques and Procedures , Madras, Dec. 1999.
  34. S.Ramachandran and S.Srinivasan, “A Programmable Pruning Level Control based MPEG Video Encoder”, International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May 2000.
  35. S.Ramachandran and S.Srinivasan, “Design and Implementation of an EPLD - based Variable Length Coder for Real Time Image Compression Applications”, International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May, 2000.
  36. S.Ramachandran and S.Srinivasan, “FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression.”, Ninth International Symposium on Field Programmable Gate Arrays , Monterey, California, USA, Feb., 2001.
  37. S.Ramachandran and S.Srinivasan, “Design and implementation of a novel, fast automatic quality control scheme-based MPEG-2 image encoder.”, World multiconference, SCI 2001 and ISAS 2001,Orlando, Florida
  38. Kavish Seth and S.Srinivasan,”VLSI Implementation of 2-D DWT/IDWT Cores using 9/7 - tap filter banks based on the Non-expansive Symmetric Extension Scheme“, Fifteenth International Conference on VLSI Design, 2002.
  39. Srikar Movva and S. Srinivasan, “A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI implementation”, Sixteenth International Conference on VLSI Design, New Delhi, India, Jan., 2003.
  40. K. Gupta and S. Srinivasan, “Reduced Memory Implementation of Modified Serial Watershed Algorithm Based on Queue”, International Conference on information Technology: Coding and Computing, Las Vegas, April 2003.
  41. A. Kishore and S. Srinivasan, “A Distributed Memory Architecture for Morphological Image Processing”, International Conference on information Technology: Coding and Computing, Las Vegas, April 2003.
  42. P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan, “A Pipelined Cellular Architecture For Euclidean Distance Transform”, TENCON-2003, Bangalore , 2003
  43. S. Ramachandran and S. Srinivasan, “Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization”, Euromicro symposium on Digital System Design, Belek, Turkey, pp. 206-213, September 2003.
  44. Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, Balakuteswar V. Voleti, “A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation” International Conference on VLSI Design, Mumbai, Jan 2004.
  45. P.Rajesh Kumar, K.Sridharan and S.Srinivasan, “An Efficient Algorithm for Topological Map Construction in a Planar Environment Explored using Proximity Sensors”, Proceedings of the Second IEEE International Conference on Intelligent Sensing and Information Processing (ICISIP 2005), pp. 67-72, Chennai, India, Jan. 2005.
  46. Kavish Seth, Viswajith, S. Srinivasan and V. Kamakoti, “Ultra Folded High-Speed Architectures for Reed-Solomon Decoders”, International Conference on VLSI Design, Hyderabad, Jan 2006.
  47. J. Sateesh Reddy, S. Ramachandran and S. Srinivasan, ?Design and FPGA Implementations of Reconfigurable Three Pass Concurrent Architectures for Embedded Block Coder and Decoder for JPEG 2000 Codec?, World Multi-conference, WMSCI 2006 and ISAS 2006, Orlando, Florida, July, 2006.
  48. K. Gaddam, N. Chandrachoodan and S. Srinivasan, “Rapid Abstract Control Model For Signal Processing Implementation”, SiPS 2007, Shanghai, China, Oct, 2007.
  49. Kavish Seth, Murali Kommishetty, Vamshi Anand, V. Kamakoti and S. Srinivasan, “VLSI Implementation of Motion Vector Recovery Algorithms for H.264 based Video Codecs,” VDAT 2009, 13th IEEE VLSI Design and Test Symposium, Bangalore, July 2009, pp. 336-346.
  50. Kavish Seth, V. Kamakoti and S. Srinivasan, “Fast Motion Vector recovery Algorithm in H.264 Video Streams,” Proc. SPIE on Multimedia on Mobile Devices, San Jose, vol. 7542, Jan 2010.
people/srini/conferences.txt · Last modified: 2010/12/24 10:35 (external edit)