I am Abhishek Bhat, PhD scholar under Prof. Nagendra Krishnapura. My research interests include design of low phase noise multiphase RF oscillators (VCO) and PLLs in bulk CMOS process. We have worked extensively on understanding flicker noise up-conversion mechanism in quadrature VCOs (QVCO) and have proposed techniques to reduce the flicker noise corner in a QVCO. The proposed technique has been validated with post-silicon results in a 130nm process. I am currently working on wide tuning range mmwave (sub 30GHz) synthesizers for 5G application.

Previous experience:

I received my B.E. degree from R.V. College of Engineering, Bangalore in 2012. Before joining IIT Madras in 2013, I worked in Cypress semiconductors, Bangalore as a Product Engineer from June 2012 to July 2013.

Publications and achievements:

1. Abhishek Bhat and Nagendra Krishnapura,“A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios”, IEEE ISSCC, 2019, San Francisco, CA, USA.
2. Abhishek Bhat and Nagendra Krishnapura, “Low 1/f^3 Phase Noise Quadrature LC VCOs”, IEEE Transactions on Circuits and Systems: Regular Papers, To appear. DOI: 10.1109/TCSI.2017.2782247.
3. Abhishek Bhat and Nagendra Krishnapura, “On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs. doi: 10.1109/TCSII.2018.2842101
4. Abhishek Bhat, Nagendra Krishnapura- “A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs” IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, May 2016.
5. Abhishek B, Abhishek G Poojary, Achuth Rao M V and S. Narayanan, “Low Power Portable EEG for Continuous Monitoring with Active Electrodes”, Proc. of TI India Educator's conference (TIEC), April 2013, pp. 332 - 339.
6. Our team of three students from R.V college of Engineering, Bangalore, was awarded second prize in- “TEXAS INSTRUMENTS ANALOG DESIGN CONTEST (2012), INDIA”, which is a national level contest on mixed-signal system design, conducted by Texas Instruments (India). (https://e2e.ti.com/group/universityprogram/w/contests/2436.contest-winners)

Patents:

1. Pending: Indian Patent file #201741033376- LOW PHASE NOISE QUADRATURE OSCILLATORS, Sep. 20, 2017.
2. Pending: Indian Patent file #201741024878- PHASE ERROR MEASUREMENT CIRCUIT WITH REFERENCELESS GAIN AND OFFSET-CALIBRATION, July 13, 2017.