• Nagendra Krishnapura

• ESB106

B slot(Mo. 9am, Tu. 8am, We. 12pm, Fr. 11am)

Registered students can login and see the course page at https://courses.iitm.ac.in/. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.

Login to moodle at https://courses.iitm.ac.in/ to post questions and contact TAs and faculty.

There will be two quizzes(30%), a final exam(40%), and regular assignments(30%).

The recorded lectures are available here. You can also find lectures from previous years at the same link.

In this course, we will discuss the design of analog circuits on integrated circuits. Realization of negative feedback circuits is a common thread to all the circuits that we see in this course. We will start with a discussion of components available on CMOS ICs, their modeling, and layout. We will then discuss noise and mismatch, which limit circuit capabilities in some ways. We then discuss negative feeback systems and their stability, and various opamp types(single stage, cascode, multi-stage, and their fully differential versions) used to realize negative feedback systems on a chip. Similar attempts to realize a frequency multiplier using negative feedback will lead us to the phase locked loop. We will analyze the main types of PLLs, and derive their incremental phase domain models commonly used for analysis. After these, we will look at bandgap references, voltage regulators, and current references as additional examples.

Problem sets will be posted below. You are expected to solve them on your own. You can approach the teaching assistants for clarifications and help. You should work each one before the corresponding dates given below.

1. Problem set 1: 2nd February 2015 (Negative feedback systems)
2. Problem set 2: 27th February 2015 (Negative feedback systems; Noise)
3. Problem set 3: 18th March 2015 (Noise, Mismatch, MOS IC components, Opamp)
4. Problem set 4: 7th April 2015 (Differential and common mode behavior, common mode loop gain)
5. Problem set 5: 22nd April 2015 (CMOS component characteristics)
6. Problem set 6: 24th April 2015 (Oscillators)
7. Problem set 7: 3rd May 2015 (Fully differential opamp; Bandgap reference)
   • Lectures 53 and 54 from the NPTEL course have a description of the bandgap reference
8. Problem set 8: 27th April 2015 (Phase locked loop-basic calculations)

The following assignments are for your practice.

1. Simulation exercises: Simulation exercises. Use the 0.18μm models from this link.

This course doesn't follow a single textbook. You can follow any of the references below for different sections of the course.

• Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, August 2000.
• Carusone, Johns, and Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2000.
• Gray, Hurst, Lewis, and Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley 2009.

This course will mostly follow the lines of NPTEL course whose link is given below.

• NPTEL course on Analog IC Design

Knowledge of negative feedback control systems is essential for a good understanding of circuits. The book below is a very good reference. Chapters 8, 9, and 10 are particularly relevant to us.

• Astrom and Murray, Feedback Systems: An Introduction for Scientists and Engineers, Available: http://www.cds.caltech.edu/~murray/amwiki/index.php/Main_Page

• Analog Circuits

If you are little rusty on basic circuit analysis or laplace transforms, refresh them from the references below or any of the widely used textbooks. In particularly, we will use Bode plots and Laplace transforms widely-they are described at the last two links below.

• Electrical and Magnetic Circuits
• Networks and Systems
• Bode plots: Recorded lectures here and here
• Circuit analysis with Laplace Transforms: Follow lectures 5-8 at this link to refresh your understanding of laplace transform analysis, sinusoidal steady state etc. Solve the practice problems in this problem set.

Attendance will be strictly enforced and those falling short will not be permitted to write the end sem exam. TAs will go around the room taking attendance at the beginning of the class. If you are more than 5 min. late, please do not enter the classroom.