• Nagendra Krishnapura

Knowledge of Fourier and Laplace transforms, feedback systems, and CMOS digital gates. Course contents

This is a self study course. Students are expected to go through the references below and understand the operation of phase locked loops and delay locked loops, block level design of the components in them, and their applications such as frequency synthesizers and clock and data recovery circuits. After this self study, you should

• know the topologies of frequency synthesizers and clock and data recovery circuits at the block level
• be able to calculate the jitter due to noise from different components.
• be able to model the above in verilogA and simulate them

• Simulation demo: 40%
• Written test: 30% (12th Nov. 2010)
• Viva: 30% (12th Nov. 2010)

At the end of the semester, you will be asked to show the simulation results(details below). You should understand why the simulation results look the way they do. In the viva, you will be tested on your understanding of what you did and general understanding of PLLs/CDRs and their building blocks. i.e. you should be able to explain why you chose the component values the way you did.

Over the course of the semester, you should study and carry out the simulations of the following. The results should be shown at the end of the semester.

• Frequency synthesizer with a multi modulus divider(250MHz output from a 5MHz reference)
• Clock and data recovery circuit using
  • Linear(Hogge) phase detector, analog loop filter and VCO
  • Bang bang phase detector, analog loop filter and VCO
  • Bang bang phase detector, digital loop filter and phase selector(32 phases)

The input to the clock and data recovery circuit should be a random rectangular bitstream at 250Mb/s passed through a filter H(s) = 1/(1+s/ωp)⁸ where ωp/2π = 250MHz

In the final setup, all components other than the VCO can be macromodels. For the VCO, use a 5 stage ring with 3 inverters loading each node(0.18um CMOS technology-get the models from CAD info page). You may use an ideal unity gain VCVS to the control port of the VCO to avoid loading on the controlling stage. For the digital CDR, use ideal sources for the 32 phases of 250MHz clock. Use verilogA in Eldo or Spectre for macro modeling. Information on simulators and device models are here.

Hints: While running simulations, initialize the control voltage of the VCO (loop filter initial condition) to the correct frequency. If the VCO starts off very far from the target frequency, it may require a long time to lock, or, in case of the CDR, may not lock at all. Monitor the control voltage to see settling. You won't be able to make out anything by looking at the VCO output. In case of the CDR, at the end of the settling period, you should plot the eye diagram of the data and the clock (for at least two data periods) and see that the clock is stably locked to the center of the data. CDR operation may initially be verified with alternating data before moving to random input data. After you verify the operation with the frequency initialized to the right value, you can try slightly shifting the target-i.e set the desired PLL or CDR output frequency to be a MHz above or below the initial frequency-and verify capture.

All references except the first one are available from IEEE Explore which can be accessed through institute proxy 10.65.0.31/32/33.

• PLLs and clock recovery circuits were covered in EE685. You can access the lectures at this link. You'll need to register with a valid e-mail address to receive the password.

• B. Razavi, “Design of monolithic phase locked loops and clock recovery circuits-A tutorial”, Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design, IEEE Press, 1996.

• von Kaenel, V. et al., “A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation,” IEEE Journal of Solid-State Circuits, Volume 31, Issue 11, Nov. 1996 Page(s):1715 - 1722
• Gutnik V. et al., “Active GHz clock network using distributed PLLs,” IEEE Journal of Solid-State Circuits, Volume 35, Issue 11, Nov. 2000 Page(s):1553 - 1560

• Craninckx, J. and Steyaert, M.S.J., “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE Journal of Solid-State Circuits, Volume 33, Issue 12, Dec. 1998 Page(s):2054 - 2065
• Y Koo et al., “A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems,” IEEE Journal of Solid-State Circuits, Volume 37, Issue 5, May 2002 Page(s):536 - 542
• Shahani, A.R.; Shaeffer, D.K.; Mohan, S.S.; Samavati, H.; Rategh, H.R.; del Mar Hershenson, M.; Min Xu; Yue, C.P.; Eddleman, D.J.; Horowitz, M.A.; Lee, T.H.; “Low-power dividerless frequency synthesis using aperture phase detection,” IEEE Journal of Solid State Circuits, Volume 33, Issue 12, Dec. 1998 Page(s):2232 - 2239

• JDH Alexander, “Clock recovery from random binary signals,” Electronics Letters, October 1975 (paper, See also page 11-12 of this paper for a brief explanation)
• C. R. Hogge, “A self correcting clock recovery circuit,” IEEE Journal of Lightwave Technology, December 1985
• Savoj, J.; Razavi, B.; “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE Journal of Solid State Circuits, Volume 36, Issue 5, May 2001 Page(s):761 - 768
• A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology Reinhold, M.; Dorschky, C.; Rose, E.; Pullela, R.; Mayer, P.; Kunz, F.; Baeyens, Y.; Link, T.; Mattia, J.-P.; IEEE Journal of Solid State Circuits, Volume 36, Issue 12, Dec. 2001 Page(s):1937 - 1945
• N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, “A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission,” IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)

• Digital CDR with digital filter and phase selection: A brief introduction to digital CDR by digitizing the operation of analog loop filter and VCO.

• Vaucher, C.S.; Ferencic, I.; Locher, M.; Sedvallson, S.; Voegeli, U.; Wang, Z.; “A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology,” IEEE Journal of Solid State Circuits, Volume 35, Issue 7, July 2000 Page(s):1039 - 1045
• Craninckx, J.; Steyaert, M.S.J.; “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS,” IEEE Journal of Solid State Circuits, Volume 31, Issue 7, July 1996 Page(s):890 - 897
• N. Krishnapura and P. Kinget, “A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS”, IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper, slides)