Dynamic range of the ADC in Compute In-Memory (CIM) is tailored to the range of the MAC over all inputs in a dataset. However, only one input is presented at a time to the CIM accelerator. My work focusses on tailioring the input range of the ADC to the conditional distribution, conditioned on the input. Tracking the mean is the key challenge in this problem. You can read more about my work here.
In compute-in-memory (CIM) macros, integrating high-precision (>7-bit) analog-to-digital converters (ADCs) with the memory array significantly increases area and energy costs. However, by exploiting the fact that only one input vector is presented to the CIM accelerator at any given time, we can use the reduced input-conditioned MAC range to achieve greater quantization precision than the on-chip ADC's native resolution. My research focuses on the design of a CIM macro chip with the central block being a cascode current mirror-based subtract and amplify circuit that enables tracking the input conditioned MAC range, giving up to 10-b precision with a 7-b on-chip ADC. For more details of my work, please refer here.
Sonu Kumar, MS (2019-)
SOI technology has been in the mainstream for high performance microprocessor design as it offers numerous advantages over conventional bulk CMOS. However, the technology suffers from significant self-heating issues due to its design. The focus of my research is to model the heat flow in interconnects for SOI devices for circuit simulators to accurately predict the performance and reliability of a circuit.
Varchas, MS(2021-)
Prathamesh Daware, MS (2023-)
Time Domain Compute In Memory architecture borrows the concept of asynchronous operation from analog signal processing while taking advantage of the inherent delay characteristics of the circuit, resulting in energy-efficient operation. It also provides unlimited "Time" accumulation, as opposed to its "Voltage" counterpart, which maintains high accuracy even for larger-length MAC operations. My research is currently focusing on Time Domain CIM hardware design for efficient and accurate AI accelerators
Karthikeyan is currently with IBM India Pvt. Ltd. in the Processor Design group. You can read about his Glitch minimization work using Geometric Programming here.
