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Vipul Bajaj

(From: Delhi College of Engineering; Texas Instruments, Bangalore)

Conference Publications

Thesis

Title: Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters

High-resolution successive approximation (SAR) analog-to-digital converters are widely used for data acquisition and seismic monitoring applications. The area and power requirements of the converter typically scale by approximately a factor of four per additional bit of resolution, primarily due to the exponential growth of the capacitor DAC (CDAC). Even with this scaling, the intrinsic matching limitations of the CDAC restrict the DC accuracy of SAR converters to approximately 12 bits. Techniques such as calibration and trimming can mitigate these limitations, but they incur significant overhead in area, cost, and test time.

This work addresses these limitations by embedding a SAR ADC in an incremental ∆Σ loop, thereby enabling the use of dynamic element matching (DEM) to improve effective linearity. The ∆Σ loop further provides quantization noise shaping, improving the overall resolution of the coarse converter. In this work, 16-bit performance is demonstrated in a 0.6µm CMOS process by implementing a first-order incremental ∆Σ loop around a 12-bit SAR ADC. The baseline SAR CDAC linearity is limited to 12 bits (DNL/INL), which is subsequently enhanced through the proposed architecture.