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Vikas Singh
(From: BIT Mesra; To: Texas Instruments, Bangalore)
Journal Publications
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay," IEEE Journal of Solid State Circuits, vol. 47, no. 8, pp. 1884-1895, August 2012.
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, "Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 676-680, Sep. 2010.
Conference Publications
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, September 2011.
Thesis
Title: Design of a High Speed High Resolution Continuous-Time Delta Sigma Modulator
Data converters are key components of almost any electronic system. Since the real world is inherently analog and the trend in telecommunication, voice, video, computer and many other applications is to get a digital form of the analog signal to make use of robust, flexible and reliable signal processing, the analog-digital interfaces become critical paths. The most interesting class of data converters is Delta-Sigma (∆Σ) modulators (DSM), which are oversampled noised shaped analog-to-digital converters (ADC). They are closed loop negative feedback converters wherein the quantization noise is high pass filtered by the loop without affecting the input signal strength. They are implemented either as continuous time (CTDSM) or discrete time (DTDSM) modulators. There are several advantages of implementing the modulator loop-filter with continuous time circuitry such as inherent anti-aliasing property, lower power consumption, higher maximum speed in a given technology. The bandwidth over which a given resolution can be achieved in a DSM is limited by the sampling frequency. For a CTDSM this sampling frequency is limited by the excess loop delay (ELD), which is one of the major concerns in high-speed continuous time (CT) ∆Σ modulators. Conventional techniques address the problem of ELD by compensating the modulator only upto half clock cycle delay, which limits the sampling rate. Our focus in this work was to come up with various circuit techniques that reduce the delay in the CTDSM loop. For example, to enable modulator operation with greater than a clock cycle delay in the quantizer, we analyze extensively the use of a parallel analog feedback path that bypasses the (slow) quantizer and enables stable modulators with quantizer delay in excess of a clock cycle. Sampling rates hitherto not possible can therefore be achieved. Additionally, a new calibration technique is introduced that removes the effect of mismatch between DAC cells without adding any extra delay in the loop. The above techniques have been applied to the design of a fourth order CTDSM with a 4 bit quantizer in 0.18 µm CMOS process. Test results of the fabricated chip show 75dB of dynamic range for a bandwidth of 16MHz. The modulator has a sampling rate of 800MHz compared to previously reported maximum of 300MHz in 0.18µm CMOS technology. The power dissipation is 47.6 mW from 1.8V supply and occupies an active area of 0.68mm. Since the technique presented here can tolerate quantizer delays of more than one clock cycle, it enables the use of multi-step quantizers, such as subranging or pipelined ADC converters, in ∆Σ modulators.