Site menu:
Shankar P
(From: College of Engineering, Guindy; To: Aura Semiconductor, Bangalore)
Conference Publications
- Shankar Parameswaran and Nagendra Krishnapura, "A 100µW Decimator for a 16 Bit 24kHz Bandwidth Audio ∆Σ Modulator," 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010.
Thesis
Title: Design of a Decimator and a Delta Sigma Modulator for Audio Bandwidth
This work explores the design of a decimator and a Delta Sigma (∆Σ) modulator for audio bandwidths. These are the essential components of the front end of a digital audio system. The first part of the work explores the design of a low power decimator and the second part of the work involves with the design of a very high resolution ∆Σ modulator.
A decimator for a low power (90µW) ∆Σ modulator with 24kHz bandwidth and an in-band resolution of 16 bits is designed in a 1.8V, 0.18µm CMOS process. To achieve a low power consumption comparable to that of the modulator, various optimizations like retiming of registers, canonical signed digits (CSD) encoding for tap weights of the filters, polyphase implementation of the filters and optimal selection of data path width are employed. The decimator occupies an area of 0.46mm² and consumes a power of 100µW from a supply of 1.8V and is operational down to a reduced supply of 0.9V.
A high resolution continuous-time ∆Σ modulator targeting a resolution of 18 bits (108dB SNR) in audio bandwidth (20Hz-24kHz) is designed in a 1.8V, 0.18µm CMOS process. The resolution of the internal quantizer is 4 bit and the modulator runs at the over sampled frequency of 3.072MHz. The modulator is designed for an SNR of 108dB and the simulated SQNR is in excess of 115dB. The modulator occupies an area of 0.89mm² and consumes a current of 540µA from a supply of 1.8V. The measured idle channel in-band integrated noise is 6.5µVrms and the modulator is stable up to -0.7 dBFS.