Nagendra Krishnapura

Rakshitdatta

(From: Sri Jayachamarajendra College Of Engineering, Mysore; To: Texas Instruments, Bangalore)

Journal Publications

Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, "A 12.5 mW, 11.1 nV/rtHz, −115dB THD, < 1 µs Settling, 18 bit SAR ADC Driver in 0.6µm CMOS," IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 63, no. 5, pp. 443-447, May 2016.
Nagendra Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 61, no. 8, pp. 2219-2228, Aug. 2014.

Conference Publications

Rakshitdatta K. S. and Nagendra Krishnapura, "On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback," 28th International Conference on VLSI Design, Bangalore, India, Jan. 2015.
Nagendra Krishnapura and Rakshitdatta K. S., "A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions," Proceedings of the 2013 IEEE Custom Integrated Circuits Conference, September 2013.

Patents

Nagendra Krishnapura and Rakshitdatta K. S., "Method for determining distortion contribution of individual elements of a circuit," Indian Patent 375099, Aug. 23, 2021.

Thesis

Title: Design and Simulation Techniques for Low Distortion Drivers for Analog-to-Digital Converters

he dissertation investigates the design of a low distortion and low noise input signal driver amplifier suitable to drive switched-capacitor loads. In particular, the work described here is directed at driving an 18-bit SAR based ADC. Such a driver, if integrated with the ADC will significantly reduce the complexity at the board level and save board space. As the driver amplifier is optimized to drive the ADC in consideration, the power dissipation at the board level will be lesser when compared to the use of general purpose opamps for realizing the driver. Many possible architectures for the driver amplifier are analyzed. Their advantages and disadvantages are pointed out.

A stand-alone driver amplifier, based on a fully-differential opamp, suitable to drive an 18-bit, 500 kS/s SAR based ADC is designed and fabricated in a 0.6 um CMOS process. Topological choices made, and various trade-offs encountered in such a design are presented. A detailed explanation of the test setup used and measurement procedures followed is given. The fabricated driver amplifier has a gain of 2 with a small-signal bandwidth of 2.5MHz. The measured rms noise at the output over a bandwidth of 20Hz-80kHz is 6.29uV. The achieved distortion performance is -119.5dB at 1kHz. The settling time for a 0.01$\%$ accurate step response with a 1 V input step is 280 ns. The chip consumes 2.5 mA of current from a 5 V supply. Measurements confirm satisfactory operation of the driver amplifier for Vdd ranging from 4 V to 6 V and for temperatures ranging between -40\degr C and +125\degr C. The performance of the driver is comparable to the Bipolar/BiCMOS parts available in the industry.

A common problem encountered during the design of circuits (especially low distortion circuits) is that of finding per-element distortion contribution. A simulation technique to find such contributions is presented. The technique is based on elementary circuit theory and can be used easily with SPICE-like simulators. It does not need the designer to extract the equivalent Taylor/Volterra series models for each of the elements. The technique is applied to a set of simple circuits and the simulation results are presented.