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Praveen M V

(From: RV College of Engineering, Bangalore; To: Maxlinear)

Journal Papers

Conference Papers

Thesis

Title: High Linearity Power Mixers for RF Transmitters

Abstract:

Class-AB power mixers used in RF transmitters have good power efficiency but poor linearity. Negative feedback with replica biasing improves the linearity but doesn't address the linearity degradation due to the drain swing of mixer baseband transistors. In this work, a direct-current sense feedback is used to directly sense the baseband current flowing into the LO switches of a Gilbert-cell mixer to further improve the linearity. A prototype chip fabricated in 0.13 µm CMOS process shows that ACLR improves by 5-8 dB for the same bias current and output power when compared to the open loop mixer. At 11.7 dBm output power, it has -41.3, -40.4, -37.6 dBc ACLR for LTE5/10/20. Noise at 80 MHz offset and 10 dBm output is -148.6 dBc/Hz. LTE10 CIM3 is -53.8 dBc at 9 dBm output power. Operating from 3 V and 1.3 V supplies, total power consumption at 11.7 dBm output is 335 mW which includes 79 mW in the LO buffers. This work achieves an efficiency of 4.4%, an improvement of 70% over the state-of-art transmitters.

Bluetooth is a short-distance wireless standard which is an integral part of cellphone platform. Hence it is imperative to improve the performance of a Bluetooth transceiver in terms of chip-area and power consumption. Bluetooth v5.0 supports data rates of 1 Mbps, 2 Mbps and 3 Mbps by employing both constant and non-constant envelope modulation schemes. Non-constant envelope modulation requires a linear transmitter. In this work, a highly linear power-mixer (which was proposed earlier) based transmitter (TX) architecture is proposed to eliminate the use of a power amplifier in the TX chain, thereby reducing the chip-area. Mixer is operated in class-AB biasing mode to reduce power consumption. An 8-bit digital to analog converter (DAC) operating at 25 MHz is integrated along with the mixer to complete the design of the entire TX chain. DAC images are attenuated by low-pass filter realized using the existing negative feedback loop around the power-mixer transconductor. The chip was designed and fabricated in a 65 nm CMOS process. TX transmits an output power of 4 dBm and 6.3 dBm for -DQPSK and GFSK modulation schemes respectively. Operating from 1.2 V/1.8 V supplies, the TX cosumes power of 50.5 mW and 62.4 mW for -DQPSK and GFSK respectively. Measured DAC image rejection is more than 48 dB at 4 dBm output power. RMS EVM for \(\frac{\pi}{4}-DQPSK\) is measured to be 8.1% and the peak EVM around 16.8%. The chip occupies an active area of about 0.49 mm2 which includes both the RF and baseband circuitry.

Class-AB power mixers typically use pseudo-differential common-source amplifiers biased near cutoff preceded by feedback controlled pre-distortion circuitry. DC bias differences between the two pseudo-differential halves of the common-source amplifiers turns out to be a major source of LO leakage. An automatic calibration method of the DC bias is proposed to reduce the LO leakage. Monte Carlo analysis shows that LO leakage is less than -35 dBc for 17% of the cases without calibration and 92% of the cases with calibration. Measurements show 14 dB reduction in LO leakage.