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Kunal Karanjkar

(From: BITS Pilani, Goa; To: Texas Instruments, Bangalore)

Conference Publications

Thesis

Title: Design of High Performance Blocks for a Hearing Aid and a Headphone Driver

The present work focusses on the design of high performance blocks for the frontend of a hearing aid and a headphone driver. The frontend blocks for the hearing aid are targeted for a low power consumption, a low input referred noise of 2 µVrms, and a high dynamic range of 108 dB. The headphone driver is targeted for a low distortion of −90 dB, and a high output swing of 1.6 V peak while driving 16 Ω load. The frontend blocks include, the programmable gain amplifier (PGA), decimation filter, low dropout regulator (LDO), and ring oscillator.

The PGA is used to amplify the input signal to a sufficiently large output signal recognized by the ∆Σ analog-to-digital converter (ADC). The gain range is from −1 dB to 40 dB with a resolution of 0.5 dB. Its input referred noise is 2 µVrms with a total harmonic distortion (THD) of −80 dB in a bandwidth of 100 Hz − 10 kHz. To achieve this low input noise at a low power consumption, a pMOS + nMOS transistor differential input pair is used in the PGA.

The decimation filter removes the shaped quantization noise at the output of the ∆Σ ADC. It reduces the sampling rate of the input signal from 2.56 MHz to 40 kHz. To achieve low power, different techniques like multistage decimation, pipelining and retiming of registers, canonical signed digits (CSD) encoding for the filter coefficients, polyphase structure, and optimal register width are used in the decimation filter.

An LDO provides a supply regulated low noise voltage for the ring oscillator and the microphone. The LDO driving the ring oscillator is a complete on-chip LDO, whereas the LDO driving the microphone is stabilized by an off-chip capacitor. The ring oscillator provides the clock to the ∆Σ ADC, the decimation filter, and the backend blocks. Since the ∆Σ ADC is a single bit with a feedback digital-to-analog converter (DAC) pulse of non-return-to-zero (NRZ), it is very sensitive to clock jitter. The oscillator's period jitter is required to be 30 ps or less in a 391 ns period.

Miscellaneous blocks for the hearing aid such as an automatic gain control (AGC) and a power-on reset (POR) are also discussed. The frontend blocks consume 144 µW of power in the 130 nm CMOS process.

The headphone driver utilizes a simple ac coupling to achieve class-AB operation in the audio bandwidth of 20 Hz − 24 kHz. It is highly linear with a THD < −90 dB for a 1.6 Vp output signal while driving a 16 Ω load. The driver is driven from a dual supply of 1.8 V and −1.8 V to avoid a large dc blocking capacitor. Furthermore, the dual supply driver can support higher output voltage swing compared to the single supply driver, thus delivering higher output power. The −1.8 V is derived from the 1.8 V using a negative voltage converter. The negative voltage converter operates at a clock frequency of 200 kHz resulting in a negative voltage conversion efficiency of 96 %. The driver consumes a quiescent power of 1 mW from the 1.8 V supply and delivers a maximum power of 80 mW to the load. The headphone driver is designed in the 180 nm CMOS process.