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Imon Mondal

(From: IIT Kanpur; To: IIT Kanpur)

Journal Papers

Conference Papers

Patents

Thesis

Title: Wideband Tunable True-Time-Delay Architecture Using a Variable Order All-Pass Filter and its Applications to Continuous-Time Pulse Processing

Abstract:

Delay lines are integral parts of wideband beamforming systems and continuous-time equalizers. Ideal delay lines can only be implemented using lossless transmission lines terminated with its characteristic impedance at both ends. A lumped element realiza- tion using an all-pass filter having linear phase can approximate a delay line within its delay bandwidth. Higher the order, more the realizable delay. However, all-pass filter architectures reported in the literature are limited to first and second order filters which can realize limited delays within a given bandwidth. Larger delays are realized by cas- coding multiple units of the lower order filters. Cascading introduces parasitic poles, thus causing distortions in magnitude or delay characteristics. This limits the maximum number cascadable unit cells, in turn limiting the maximum achievable delay.

This thesis proposes an all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits. Using this a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product is demon- strated. This is useful for beamforming and equalization in the lower GHz range where the use of LC or transmission line based solutions to realize large delays is infeasi- ble. Coarse tuning of delay is realized by changing the filter's order while keeping the bandwidth constant and fine tuning is implemented by changing the filter's bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13µm CMOS process demonstrates a delay tuning range of 250 ps-1.7 ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a delay-bandwidth product of 3.4 and a delay per unit area of 5.8 ns/mm2. The filter has a worst case noise figure of 20 dB, and -40 dB IM3 distortion for 37 mVppd inputs. The chip occu- pies an active area of 0.6 mm2 and dissipates 112 mW-364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced by 7.5 cm (half wavelength at the maximum frequency of 20 GHz) shows ±900 beam steering off broadside.

Exploiting the feasibility of large delay-bandwidth product of this architecture, a high order all-pass filter has been used to demonstrate true-time expansion and compres- sion of narrow, wideband, finite width, continuous-time pulses. It is based on storing an input pulse as state-variables in a continuous-time filter whose delay exceeds the pulse duration, and, once the pulse is completely "inside" the filter, reducing or increasing its bandwidth. Expansion and compression enable processing and generation of high speed pulses using low speed circuits. The proposed method can be implemented on an IC unlike photonic or microwave implementations based on dispersive media. It is more accurate and less complex than IC implementations using a high frequency chirped VCO and on-chip group delay dispersion. It avoids high speed sampling and is more immune to jitter than sampling the signal on a capacitor array. Pulse expansion and compression by factors of 1.8× and 1.7× respectively are demonstrated in a 0.13µm CMOS process. The prototype chip includes a filter whose bandwidth can be switched between 870 MHz and 472 MHz and circuitry to generate Gaussian/monopulse for test- ing. It occupies 1.6 mm2 and consumes 370 mW.