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Debasish Behera
(From: IIT Madras, Marvell; To: Aura Semiconductor, Bangalore)
Journal Publications
- R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3651-3661, Nov. 2018.
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay," IEEE Journal of Solid State Circuits, vol. 47, no. 8, pp. 1884-1895, August 2012.
Conference Publications
- R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, "Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion," The International Symposium on Integrated Circuits and Systems (ISICAS), Taormina, Italy, Sep. 2018.
- Debasish Behera and Nagendra Krishnapura, "A 2-Channel 1MHz BW, 80.5dB DR ADC Using ∆Σ Modulator and Zero-ISI Filter," Proceedings of the 40th European Solid-State Circuits Conference, Venice, Italy, Sep. 2014.
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, and Debasish Behera, "A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay," Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, September 2011.
Thesis
Title: Memoryless Analog-to-Digital Conversion Using ∆Σ Modulator and Zero-ISI Filter
In many applications such as industrial automation or multiple-sensor data acquisition, many analog inputs need to be efficiently digitized with good matching between different channels. An analog multiplexer followed by a single ADC provides a compact solution with good matching between channels, and is usually the preferred solution in such cases. In such an environment, the ADC needs to have zero inter-symbol interference (ISI), i.e. provide sample-by-sample conversion. Nyquist rate architectures like SAR or pipeline ADCs fit the bill, but, rely on analog component matching and require calibration for high resolution. ∆Σ ADCs provide higher resolution compared to Nyquist ADCs due to oversampling and noise shaping. But they suffer from memory and cannot be used directly in multiplexed input applications. Traditional solutions either share hardware among multiple channels or reset the ∆Σ ADC to obtain sample-by-sample conversion. But these solutions significantly compromise the signal bandwidth. In this work, it is shown that memoryless conversion is possible without resetting the modulator or decimation filter by using a suitable signal transfer function for the modulator and a decimation filter which satisfies Nyquist zero ISI criterion. This architecture enables memoryless operation over the entire signal bandwidth of the ∆Σ ADC which is significantly higher than the existing solutions. The technique breaks the trade-off between the length of the decimation filter and the Nyquist rate of the converter.
The technique is demonstrated in a 0.18 µm process. A two-channel ADC with a total effective sampling rate of fs/64 per channel is built using a third order 32× oversampled switched-capacitor ∆Σ modulator. In standalone mode it achieves 86.5 dB and 85.1 dB DR at 16 MHz and 64 MHz sampling rate respectively. In two-channel mode, with per-channel rate of 250 kHz the DR is 81 dB and for 1 MHz the DR is 80.5 dB. At both sampling rates, the inter-channel crosstalk due to maximum input on the other channel is below 77.7 dB.