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Chithra

(From: BITS Pilani Goa; To: IIT Kanpur)

Journal Papers

Conference Papers

Patents

Thesis

Title: A Multi-Hit Multi-Channel Time-to-Digital Converter for the India-based Neutrino Observatory

Abstract:

KEYWORDS: Time-to-digital converter, multi-channel TDC, India-based neutrino observatory, particle detector, trigger-based data acquisition, delay-locked loop, system-level modeling, single-shot precision, static phase offset.

A time-to-digital converter (TDC) is a circuit that can measure time intervals with very high resolution. This thesis presents a multi-channel time-to-digital converter de- signed for the iron calorimeter detector in the India-based neutrino observatory. The TDC records the time instants at which a particle of interest is sensed within the de- tector, thereby aiding the track reconstruction of the particle. The TDC, designed in a 130nm CMOS process, has a resolution of 125 ps, dynamic range of 65.5 µs, and can store the timestamps of the latest 4 events in each channel. The TDC has 17 hit channels and 1 trigger channel, and is compatible with a trigger-based data acquisition system.

The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. Circuit nonidealities that affect the TDC performance, such as incorrect DLL locking, mismatches in devices, skew between the coarse and fine TDC, and duty cycle variation in the clock phases are analyzed, and the solutions are discussed. The generation of the final timestamp customized for the detector’s data acquisition system is implemented within a digital backend. This backend also controls the TDC configuration and implements the communication protocol for interfacing with an external controller. The common core to all channels with concurrent accessibility, choice of core clock frequency optimizing the trade-offs between performance, power and area, and optimal backend logic result in a compact and low power design.

Thorough system-level verification of this design proved to be a challenge due to the long simulation run times. By modeling the analog circuits in Verilog, full system simulation run-time was reduced to < 1 min. The verification time was further improved by capturing the TDC functionality into behavioral models, thereby enabling a self-checking testbench. These modeling techniques allowed the automation of the verification process and ensured a faster design closure.

Measurement precision is an important parameter for any electronics part of the detector set up. This thesis reviews the theory on how timing precision is defined for a single-shot TDC and explains how the TDC characterization test plan can be devised based on the jitter in the system.

The TDC prototype designed in 0.13 µm CMOS process, achieves a single-shot precision better than 65ps. The measured differential nonlinearity (DNL) varies from -0.27LSB to 0.21LSB, while integral nonlinearity (INL) varies from -0.19LSB to 0.25LSB. The TDC occupies an active area of 3.72mm2 and consumes 3.4mW per channel.

Static phase offset is one of the delay-locked loop nonidealities that affects the linearity of a high-resolution TDC. This parameter is undesirable in most of the DLL- based circuit designs. Artifacts in the phase-frequency detector (PFD) and the charge pump contribute to static phase offset in the DLL. Chopping, which is a well-known technique for offset reduction, can be easily applied to the PFD. Applying it to the charge pump is non-trivial and requires complex circuitry. We propose a new technique that reduces the offset due to both PFD and the charge pump without actually chopping the latter. Analysis of the proposed method shows an offset reduction at least by a factor of 2. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9ps in the conventional technique to 1.7 ps in the proposed technique.