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Chembiyan Thambidurai

(From: BITS Pilani; To: Aura Semiconductor, Bangalore)

Journal Publications

Conference Publications

Thesis

Title: On Pulse Position Modulation and its Application to PLLs for Spur Reduction

Phase lock loops (PLLs) are used in frequency synthesis for modulation and demodulation of base band data in wireless communications and to generate clocks for accurate timing in digital systems like microprocessors. One class of PLLs called the charge pump PLLs has gained wide popularity due to its relative ease of implementation. However due to the discrete time nature of the phase frequency detector and nonidealities in the charge pump, a periodic charge pump current is injected into system in the steady state. This results in spurs in the output spectrum of the PLL. The bandwidth of the PLL is reduced to have low spur levels. A lower PLL bandwidth increases the settling time of the PLL and reduces the frequency range of rejection of the VCO phase noise.

The central idea of this work is to break the periodicity and convert the energy in the spurs into a wideband noise, which enables the PLL to have larger bandwidth and maintain low spur levels. Randomizing the positions of charge pump current pulses in a PLL breaks their periodicity and redistributes the reference spurs into broadband noise. In this work closed form expressions for the spectrum of pulse position modulated (PPM) signals are derived and intuitive explanations for the results are given. The redistributed noise has a highpass shape and does not affect the close in phase noise of the PLL. PPM using a uniformly distributed uncorrelated sequence completely removes the spurs and provides a first order shaping of redistributed noise. Higher order shaping and reduction of redistributed noise at intermediate offset frequencies are possible using PPM with a correlated modulating sequence and pulse repetition. Circuit implementations of these techniques are given and their nonidealities are discussed. The implementation ideas proposed in this work leads to a compact implementation of the techniques and is more insensitive to delay mismatch. A detailed analysis of the delay line nonidealities is also presented to study their effect on the PLL output phase noise.

Simulation results confirm the results of the analysis and viability of the proposed techniques. In the presence of nonidealities spurs can be reduced by at least 13 dB without any trimming of the delays in the PPM circuits and by 25 dB after trimming the delays within 5% of the nominal value.

A 1 GHz PLL operating from a reference frequency of 20 MHz and a bandwidth of 1 MHz is implemented in 0.18 µm CMOS technology to test the proposed ideas. The spur at −20 MHz offset from the carrier (980 MHz) was measured to be 64 dBc. Enabling the PPM and PR reduces the magnitude of the spur by 8 dB and 9 dB respectively.