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Aswani Kumar Unnam

(From: QIS College of Engg. and Tech.; To: Qualcomm, Bangalore)

Journal Publications

Thesis

Title: Design of Higher-order Multi-Bit Incremental Continuous-time Delta-Sigma ADCs for Medium Bandwidth and Resolution

Incremental continuous-time delta-sigma ADCs (ICTDSM) are gaining popularity in applications requiring sample-to-sample conversion, such as in multiplexing scenarios. The resistive input impedance of ICTDSM simplifies the driver design, which is crucial in multiplexing scenarios where step jumps in voltages occur at the start of each conversion cycle, and power consumption is a concern. In an ICTDSM, all memory elements and capacitors are reset at the beginning of the conversion cycle to enable sample-to-sample conversion. However, when there is excess loop delay (ELD) in the loop, integrators operate in the open loop in the first cycle after reset until a stable input is available to the DAC. This leads to saturation of the integrators and quantizer and reduced maximum stable amplitude (MSA). Conventional DAC mismatch shaping algorithms like data weighted averaging (DWA) are inefficient in higher-order ICTDSMs and require complex algorithms, further limiting their performance in high-speed applications and adding more delay to the loop, which worsens stability. Hence, ICTDSMs have been limited to low speeds and lower orders.

This work addresses these limitations by proposing a modified reset topology that improves the linearity of the loop filter even with ELD and limits the swings of the integrators, thereby improving stability. Additionally, calibration is employed instead of data weighted averaging (DWA) to tackle digital-to-analog converter (DAC) mismatch, and the proposed calibration is implemented in the background without adding extra delay to the loop. The prototype ADC designed in a 180 nm CMOS technology using the above techniques achieved 81.9 dB signal-to-noise and distortion ratio, 84.5 dB signal-to-noise ratio, 90 dB dynamic range in a bandwidth of 2.5 MHz with the modulator operating at 320 MHz, i.e., a conversion duration of 64 cycles. To the best of our knowledge, this is the highest bandwidth reported for an incremental continuous-time delta-sigma ADC. These results demonstrate the effectiveness of the proposed approach in overcoming the limitations of ICTDSM and enabling high-speed ADCs for practical applications.