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Ashwin Kumar

(From: CEG, Chennai; To: IIT Kanpur)

Journal Papers

Conference Papers

Patents

Thesis

Title: Multi-Channel Analog-to-Digital Conversion Techniques Using a Delta-Sigma Modulator

Abstract:

KEYWORDS : Delta-sigma modulators, multi-channel ADC, incremental DSM, Nyquist filter, equalization, adaptive equalizers.

High-resolution analog-to-digital converters are realized using a delta-sigma modulator (DSM). However, the intrinsic memory present in the delta-sigma ADC due to the signal transfer function of the modulator, and the decimation filter, prevents it from being used as a multi-channel ADC. The conventional solution to this problem is to use an incremental delta-sigma ADC, where the memory elements in the ADC are reset before the start of every conversion cycle. However, this intermittent operation reduces the achievable signal-to-quantization noise ratio (SQNR), and signal-to-noise ratio (SNR).

This work proposes new techniques that let a continuously running delta-sigma ADC to perform multi-channel analog-to-digital conversion without reset. First, it is shown that, using a sample-and-hold operating at the Nyquist rate before a delta-sigma ADC, makes the overall system linear-time-invariant. This enables the use of an equalizer with the inverse transfer function so that the overall system is now memoryless. In order to track the variations in the analog transfer functions of the sample-and-hold and that of the modulator, the equalizer is made adaptive. Using this technique, a two-channel ADC using a discrete-time DSM is designed in UMC 180 nm CMOS process. Clocked at 32 MHz with an oversampling ratio of 32, it consumes 16.36 mW/channel from a 1.8 V supply and achieves an SNR/SNDR/DR of 82.5 dB/80.1 dB/84.2 dB. The inter-channel cross-talk is less than −86 dBc across the whole bandwidth of 250 kHz.

To reduce the power consumption, the discrete-time DSM is replaced by a continuous-time DSM (CTDSM), and a two-channel CTDSM prototype is designed. Running at 6.144 MHz with a channel bandwidth of 24 kHz, the CTDSM prototype draws 1.33 mW per channel from a 1.8 V supply. The measured SNR/DR is 91.7 dB/98 dB, and the cross-talk is less than −77.7 dBc over the entire signal bandwidth.

A new method is then proposed, where it is shown that, for a two-channel ADC, to avoid cross-talk at the output, instead of an equalizer that enforces an overall flat frequency response, it is both sufficient and necessary to ensure that the overall frequency response is symmetric about ω = π/2. This is possible by using the proposed “π-shifted filter”. The corresponding filter required for an N-channel ADC is also derived. The order of this proposed filter is found to be lower than that of the adaptive equalizer, used to force an overall flat frequency response. Hence this filter consumes a lower power than the adaptive equalizer. This technique is tested with the CTDSM prototype and the cross-talk improved to less than −80.1 dBc. Simulations show that the π-shifted filter with the decimation filter consumes 66% lower power than the adaptive equalizer with the decimation filter in this prototype. The measured SNR/DR is 90.5 dB/97 dB.

The overall system performance in the above methods was mainly limited by the active sample-and-hold used before the delta-sigma ADC. So a circuit technique is proposed that replaces this active sample-and-hold by a passive sample-and-hold. This avoids the extra power consumption in the S/H, thereby improving the performance. On the downside, this technique makes the layout difficult, especially for higher oversampling ratios.

The main drawback of the above methods was the requirement of a circuit that acts as a Nyquist-rate S/H. A new method is then proposed that eliminates the front-end sample-and-hold altogether. With this method, any existing delta-sigma ADC can be converted to a multi-channel ADC only by adding the proposed “modulated-sinc-sum” digital filter at the output. The advantage of this method is that, it neither requires any changes to be made to the delta-sigma ADC nor does it require any extra analog blocks, making this the simple and the most efficient solution. It is shown that this is at least 4 dB more power efficient compared to the incremental delta-sigma ADC. To demonstrate the proposed technique, a two-channel ADC is designed and fabricated in UMC 180 nm CMOS process. Clocked at 6.144 MHz, the designed ADC has a channel bandwidth of 22 kHz, and consumes 1.53 mW/channel from a 1.8 V supply. The measured SNR/DR is 94.4 dB/98.5 dB, respectively. The measured inter-channel cross-talk is less than −94 dBc across the entire bandwidth.