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Aritra Chowdhury
(From: IIEST Shibpur; To: Texas Instruments, Bangalore)
Thesis
Title: Design of Low Area 6 bit Subranging and SAR Analog-to-Digital Converters for Microcontrollers
The high resolution (12–16 bits) Nyquist analog-to-digital converters (ADC) with moderate speed (16 MS/s) and multichannel inputs are prevalent in commercial microcontrollers (C2000 family of MCUs of Texas Instruments). At this resolution and speed, it is convenient to use a two-step approach, which breaks the high resolution conversion into a coarse medium resolution ADC followed by a fine ADC. In this work, we have explored possible ADC architectures to realize the coarse ADC. Our goal is to increase the resolution yet reduce the area from the commonly used solutions, which employ the flash architecture.
The flash topology suffers from the drawback of exponential growth in the area with the resolution. The 6 bit 25 MS/s subranging ADC, exploiting the multi-bit binary search mechanism, is designed as an area efficient architecture. The practical implementation issues of this topology limit the worst conversion time to 19.05 ns. The designed ADC consumes 9810 µm² area. As an attempt to improve the latency, 6 bit 25 MS/s asynchronous successive approximation (SAR) ADC has been implemented, which employs single-bit binary search. The designed SAR ADC consumes 20742 µm² area with the simulated worst conversion time of 10.5 ns. Both these architectures are fabricated in 65 nm CMOS technology.