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Anoop Bhat
(From: RV College of Engineering, Bangalore; To: Texas Instruments, Bangalore)
Journal Publications
- N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3531-3543, Sept. 2019.
Conference Publications
- N. Krishnapura, A. N. Bhat, S. Mukherjee, K. A. Shrivastava and M. Bonu, "Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables," The International Symposium on Integrated Circuits and Systems (ISICAS), Venice, Italy, Aug. 2019.
- Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, "A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS," 2017 International Solid-State Circuits Conference, San Francisco, USA, Feb. 2017.
Thesis
Title: A Power Efficient CMOS Receiver for OOK Wireless Link
The symbol rate of a communication channel of given bandwidth is limited by inter-symbol interference (ISI) for required bit error rate (BER). Data rate of such a communication system can be increased by increasing the signal-to-noise ratio of the signal and then using multilevel signaling (increasing number of bits per symbol) or equalization. Both of these techniques increase circuit complexity in the transmitter and receiver.
We propose a technique of data rate enhancement in chip-to-chip wireless communication using simple on-off keying (OOK) modulation. The technique involves periodic resetting (correlated to input data) of the channel accessible to transmitter and receiver. This technique of data rate enhancement proves to be more power efficient and has simpler transmitter and receiver circuitry compared to the other two techniques. The proposed technique achieves a data rate of 500 Mbps using OOK modulation with 2 GHz carrier frequency through a bandpass channel of 130 MHz bandwidth centered at 2 GHz. This is about four times the data rate that is possible with traditional OOK through such a channel.
In this work a receiver is designed to evaluate the proposed idea. The receiver consists of two-stage programmable gain amplifier (PGA), a peak detector to demodulate the signal, a comparator to convert the analog signal into bits, and a delay and reset generation block to reset the channel accessible to receiver. To maximize the detected signal amplitude, a peak detector which operates on both positive and negative input signal peaks is used. A biasing technique for the peak detector is proposed in which the dc offset of the peak detector output can be set independently of supply voltage, process and temperature variations.
Receiver circuit is fabricated in 180 nm CMOS process and tested. It occupies an area of 0.8 mm × 0.6 mm. A data rate of 500 Mbps is achieved with 5.6 mW power consumption (11.2 pJ/bit). Measurements show that the proposed reset technique nearly doubles the horizontal eye opening for a BER of 10⁻⁸ at a data rate of 300 Mbps.