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Ananya Senapati
(From: BITS Pilani Hyderabad; To: Aura Semiconductor, Bangalore)
Conference Publications
- A. Senapati and N. Krishnapura, "Design Considerations for a Closed-loop Digital Class-D Audio Amplifier," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5.
Thesis
Title: Design of a Closed-loop Digital Class-D Amplifier for Portable Audio Devices
Class-D amplifiers have become the preferred choice in battery driven portable audio devices for their high power efficiency. However, the total harmonic distortion plus noise performance of an open-loop class-D amplifier is limited by the nonidealities of its switching output stage. The commonly used approach to alleviate this problem is to enclose the output stage in a negative feedback loop. Traditionally, the elements in the feedback loop, i.e., the loop filter and the pulse width modulator, are implemented in analog domain. Today, with the audio formats being digital, a high performance digital-to-analog converter is used in the front-end to convert the digital audio input to analog prior to feeding the analog class-D loop. However, in a signal chain with digital input, it is advantageous to keep the signal digital as long as possible, as digital blocks are robust across process and temperature variations and are easily portable across technology nodes. Hence, this work focuses on the design of a digital closed-loop class-D amplifier, where the loop filter and the pulse width modulator are implemented digitally. A high performance analog-to-digital converter samples and feeds the digitized analog output of the power stage to the digital.
The challenges involved in the design of the system are discussed. Derivation of individual block specifications and the design steps are presented. The amplifier is designed to deliver an output power of 4 W to an 8 Ω speaker load. The switching frequency of the power stage is 384 kHz. The digital pulse width modulator operates with a clock frequency of 24.576 MHz. An existing continuous time delta-sigma analog-to-digital converter having a sampling frequency of 6.144 MHz and an oversampling ratio of 128 is used in the system. The system achieves a peak signal to noise plus distortion ratio of 93 dB in a bandwidth of 20 kHz from simulation. Analysis of the measured performance of the system is presented.