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Aditya Narayanan
(From: IIITDM Kanchipuram; To: Texas Instruments, Bangalore)
Journal Papers
- A. Narayanan, A. Bhat and N. Krishnapura, "A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays," in IEEE Journal of Solid-State Circuits, vol. 59, no. 9, pp. 2818-2830, Sept. 2024.
- Chithra, A. Narayanan, R. S. A. Kumar and N. Krishnapura, "Auto-zeroing Static Phase Offset in DLLs using a Digitally Programmable Sensing Circuit," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1788-1792, June 2021.
Conference Papers
- A. Narayanan and N. Krishnapura, "Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs," 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, 2023, pp. 1-5.
Patents
- Aditya Narayanan and Nagendra Krishnapura, "System and method of mitigating divider delay variations in a fractional frequency synthesizer," Indian patent 572897, 29 October 2025.
Thesis
Title: Design Techniques for Wide Tuning Range Fractional-N Phase-Locked Loops.
Abstract:
KEYWORDS : Phase-locked loop (PLL); fractional-N PLL; voltage-controlled oscillator (VCO); inductor switching; feedback-divider; modulus-dependent-divider delay; digital delta-sigma modulator (DDSM); predistortion; integer-N PLL; sub-reference spur
When an octave tuning range phase-locked loop (PLL) operates from a fixed reference frequency, the feedback division modulus has to change by a factor of two. This effectively means that the divider chain has to use a variable number of stages. The delay of the feedback divider varies with the modulus setting. The variation can exceed 100 picoseconds when the number of stages is changed. For fractional-N operation, the division modulus is varied dynamically. Thus, the feedback divider’s delay changes dynamically and by a large amount when there is a change in the number of stages used. This results in quantization noise folding, which increases the phase noise/jitter and fractional spurs. Solutions to this problem proposed in the literature include (a) Resynchronizing the divider output to divider input; This may need delay locking to ensure proper operation of the resynchronizing flip-flop over process corners, (b) Using the divided signal from the feedback path of the divider chain; There is still residual delay variation in this case, which can degrade spurious performance. Realizing resynchronization may typically involve multiple schematic-layout iterations to avoid metastability of the resynchronization flip-flop across PVT.
This work proposes a digital technique that bypasses resynchronization to counter divider delay variation. The variable delay of the division modulus can be tackled by appropriately predistorting the fractional input to the digital delta-sigma modulator (DDSM) used for fractional-N synthesis. There are two variants of this solution. The first is to use a predistortion sequence that exactly cancels (at low frequencies) the effect of modulus-dependent delay on the output phase noise. This requires knowledge of the modulus dependent delays. A time-to-digital converter (TDC) can be used to measure the modulus dependent delays and determine the predistortion sequence in a foreground calibration scheme. The second is to use a predistortion sequence that turns the effect of modulus-dependent delay into a periodic phase error at the PLL output. This can be used when the divider delay is binary valued. This happens when the delay change is mainly due to change in the number of divider stages. With the proposed technique, instead of increased jitter, the delay variation results in a tone at half the reference frequency that can be filtered to a sufficiently low value with typical loop filter bandwidths. This technique is independent of PVT variations and does not need knowledge of the delay values. The thesis presents a PLL that demonstrates the proposed solution.
The prototype PLL generates quadrature LO waveforms covering an octave range of 6–12 GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). The prototype synthesizer in 65 nm CMOS occupies 0.54 mm² and consumes 66 mW at the highest frequency from a 1 V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400 fs, 300 fs, 500 fs in the 6–8, 8–10, and 10–12 GHz ranges, respectively. The worst-case reference spurs are below −60 dBc and the fractional spurs are below −31 dBc.
The thesis also presents the design of an integer-N frequency synthesizer operating from 2.4 to 2.48 GHz with a channel spacing of 1 MHz, for compliance with Bluetooth standard. Simulating the phase noise contribution of the feedback divider is not straightforward due to the large division modulus. A method is outlined by which the divider’s output phase noise can be accurately determined by simulating stages of the divider one at a time. In addition, a mechanism that causes sub-reference spurs in integer-N PLL and possible remedies are discussed.