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Abhishek Bhat
(From: RV College of Engineering, Bangalore; To: Cisco)
Journal Papers
- A. Narayanan, A. Bhat and N. Krishnapura, "A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays," in IEEE Journal of Solid-State Circuits, vol. 59, no. 9, pp. 2818-2830, Sept. 2024.
- A. Bhat and N. Krishnapura, "A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 160-171, Jan. 2022.
- Abhishek Bhat and Nagendra Krishnapura, "On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 162-166, Feb. 2019.
- Abhishek Bhat and Nagendra Krishnapura, "Low 1/f3 Phase Noise Quadrature LC VCOs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2127-2138, July 2018.
Conference Papers
- Abhishek Bhat and Nagendra Krishnapura, "A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios," 2019 International Solid-State Circuits Conference, San Francisco, Feb. 2019.
- Abhishek Bhat and Nagendra Krishnapura, "Low 1/f3 Phase Noise Quadrature LC VCOs," Proc. 2018 International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence, Italy.
- Abhishek Bhat and Nagendra Krishnapura, "A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs," Proc. 2016 International Symposium on Circuits and Systems (ISCAS), pp. 2070-2073, 22-25 May 2016, Montreal, Canada.
Patents
- Abhishek Bhat and Nagendra Krishnapura, "Low phase noise quadrature oscillators," Indian patent 558513, 22 January 2025.
- Abhishek Bhat and Nagendra Krishnapura, "Phase error measurement circuit with referenceless gain and offset calibration," Indian Patent 487682, 22 December 2023.
Thesis
Title: Low Phase Noise Quadrature Carrier Synthesis for Millimeter-Wave and Low-GHz Radios
Abstract:
Frequency synthesizers with quadrature outputs are integral to modern high-performance direct conversion transceivers. Generating low phase noise quadrature carriers with low power consumption is challenging due to the limited quality factor of the on-chip inductors and capacitors at RF and millimeter-wave frequencies in a bulk CMOS process. The inherent flicker noise in MOS transistors used in the oscillator further degrades the phase noise of the carrier, which makes the design of the oscillator even more challenging. Also, obtaining a sufficient frequency tuning range to cover multiple frequency bands in an oscillator is challenging especially at millimeter-wave frequencies due to the poor quality factor of the programmable capacitors and inductors.
This thesis studies the flicker noise upconversion mechanism in coupled LC quadrature voltage controlled oscillators (QVCO) and proposes new circuit topologies which significantly reduce the noise upconversion in a QVCO. 2.4 GHz prototypes of two of the proposed QVCOs in a 0.13 µm CMOS process have 1/f3 phase noise corners of 400 kHz and 150 kHz compared to 3 MHz in the conventional QVCO. The measured figures of merit of the proposed QVCO prototypes are 190.2 dB and 193.2 dB. These are significantly higher than 183 dB which is the measured figure of merit of a conventional QVCO prototype designed in the same process.
Phase errors in the generated quadrature carriers degrade the performance of the transceiver. To measure and calibrate the phase errors on-chip, a gain- and offset-calibrated 3-state phase detector is proposed to accurately measure static phase difference. A 0.13 µm CMOS prototype of the proposed enhanced phase detector has errors ≤ 0.5° for 2.4 GHz quadrature inputs. It consumes 3.6 mA from a 1.2 V supply and occupies 0.0416 mm². The proposed circuit can also be used for on-chip measurement and calibration of any multi-phase clock generators in radios and clocking circuits.
The thesis also studies the challenges in attaining wide frequency tuning range in millimeter-wave VCOs and proposes a millimeter-wave quadrature VCO using two resonant modes of a 4-port coupled inductor in a 65nm LP bulk CMOS process. The QVCO tunes from 25 GHz to 38 GHz while consuming 17.5 mW to 21.6mW from a 0.65V supply. The resonator structure is symmetric, uses single-turn coils, and has short interconnections to active circuits. The QVCO exhibits an excellent average tuning range FoM (FoMT) of 195 dB.
Designing small area phase-locked loops (PLL) for millimeter-wave applications is challenging, due to the large area occupied by the loop filter of the PLL. This thesis proposes a new capacitor-only low area loop filter for a class of PLLs called sub-sampling PLLs, with 25x reduction in required loop filter capacitor when compared to the con- ventional one. The proposed PLL maintains a jitter-FoM of > 235 dB.