Abstract: Wideband spectrum sensors face a fundamental linearity-sensitivity tradeoff that no conventional single-path receiver can break: improving linearity through input attenuation directly degrades the noise floor.

This work presents the design validation and performance assessment of a fully integrated cross-correlation spectrum analyzer in 65 nm CMOS that resolves this impasse by splitting the input across two independent receiver paths and averaging their cross-power spectral density to suppress uncorrelated receiver noise as 5log₁₀(m) dB. The 4.83 mm² chip integrates the complete signal chain on a single die — RF front-end, baseband, 8-bit ADCs, and a digital back-end with on-chip power estimator — and is designed to operate from 300 MHz to 6 GHz with three programmable gain settings; post-silicon characterization covers the 800 MHz to 4 GHz band, bounded by external limitations rather than by the silicon itself. An off-chip FPGA backend performs cross-correlation averaging, digital harmonic folding cancellation, and I/Q mismatch correction on the streamed ADC data. Measured performance includes a peak SFDR of 70 dB, IIP3 of +1.5 dBm, correlated noise figure as low as 8 dB, and sensitivity down to −86 dBm, with the chip drawing 220 mW from 1.2 V/1.8 V supplies.

Event Details
Title: Design Validation and Performance Assessment of an 300 MHz to 6 GHz Cross-Correlation CMOS Spectrum Analyzer
Date: June 09, 2026 at 02:00 PM
Venue: ESB 210B
Speaker: Mr. Rahul M (EE23S049)
Guide: Dr. Shanthi Pavan
Type: MS seminar

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