Design, Characterization, and Calibration of Continuous-Time Pipelined Analog to Digital Converters (PhD Viva Voce)

Abstract: This work presents the design and experimental validation of Continuous-Time Pipelined (CTP) ADCs, a scalable architecture that combines the anti-aliasing and noise-shaping benefits of continuous-time systems with the modularity of pipelined converters.

To tackle the challenges introduced by the proposed architecture, this work presents new techniques for digital reconstruction, calibration, and testing. Hardware-efficient foreground and background calibration schemes are developed to ensure robust operation across temperature variations without requiring power-intensive reconstruction-filter recapture algorithms. Additional methods to improve resilience to Nyquist-band inputs, along with sub-DAC mismatch calibration, further enhance signal handling capability and converter accuracy. These techniques are demonstrated in a 65 nm CMOS implementation of a CTP ADC. The proposed prototypes achieve up to 73.5 dB SNDR over a 100 MHz bandwidth at 800 MS/s, highlighting the potential of CTP-ADCs as robust, power-efficient, and scalable solutions for wideband data conversion.

Event Details
Title: Design, Characterization, and Calibration of Continuous-Time Pipelined Analog to Digital Converters (PhD Viva Voce)
Date: June 09, 2026 at 10:00 AM
Venue: Google Meet (https://meet.google.com/djz-ndqn-pny)
Speaker: Mr. Nishanth Basavaraj (EE20D701)
Guide: Dr. Shanthi Pavan
Type: PHD seminar