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Phase Lock Loops and Clock and Data Recovery Circuits-Self study course

Co-ordinator: Nagendra Krishnapura


Office : ESB246B
Office hours : Tue. & Thu. 1600-1700
E-mail : nagendra AT iitm.ac.in
Phone : 4444
web page : http://www.ee.iitm.ac.in/~nagendra/EE480/current/index.html

Prerequisites

Knowledge of Fourier and Laplace transforms, feedback systems, and CMOS digital gates.


Course contents

This is a self study course. Students are expected to understand the operation of phase locked loops and delay locked loops, block level design of the components in them, and their applications such as frequency synthesizers and clock and data recovery circuits. After this self study, you should

You can learn about all of these by going through the references below.

At the end of the semester, you should show simulations of the following Frequency synthesizer with a multi modulus divider(500MHz output from a 1MHz reference) Clock and data recovery circuit(500Mb/s input with a closed eye) using a) Linear phase detector, and b) Bang bang phase detector

In the final setup, all components other than the VCO can be macromodels. For the VCO, use a 5 stage ring with 3 inverters loading each node(0.18um CMOS technology). Use verilogA in Eldo or Spectre for modeling.


Evaluations

Your grade will be based on the demonstration of the simulation results and a viva, to be held at the end of the semester.


References

All these references are available from IEEE Explore which can be accessed through institute proxy 10.65.0.31/32/33.

Overview

Clock generation

RF frequency synthesizers

Clock and data recovery

Frequency dividers


Simulation

Macromodeling can be done using verilogA in Eldo or Cadence/Spectre. For setup and usage of Eldo, see this page. Eldo's verilogA documentation can be found at $anacad/documentation/eldo_vloga.pdf. Cadence's verilogA documentation can be found at $CDS_INST_DIR/doc/veriaref/veriaref.pdf