The project aimed at conducting studies to establish the viability of designing and implementing circuit blocks that form part of a Digital Signal Processor (DSP). A Multiplier-Accumulator (MAC) module was taken up as the best example for providing us with the necessary insight into the design and implementation of such blocks.

Parallel iterative multipliers have a homogeneous structure which is ideal for modular VLSI. implementation and so some of the parallel iterative multipliers were taken up for studies with particular reference to speed and complexity. Implementation of the MAC was carried out for two best algorithms, viz., the Baugh Wooley algorithm and the modified Booth's algorithm. When mapped to Xilinx XC3000 family FPGAs, the Baugh Wooley multiplier required almost double the number of cells compared to modified Booth's multiplier of the same speed. As the project was completed much ahead of schedule, the scope of the project was enlarged and two 16 X 16 MACs were developed using XC 3000 and XC 4000 series FPGAs.