By S. Ramachandran

KEYWORDS:Discrete Cosine Transform, Variable Length Coding, Pruning Level, Automatic Quality Control Scheme, Motion Estimation and Compensation and Field Programmable Gate Array.

Raw image data used in applications such as high definition television, video conferencing, computer communication, etc. require large storage and high speed channels for handling huge volumes of image data. In order to reduce the storage and communication channel bandwidth requirements to manageable levels, data compression techniques are inevitable. It is of paramount importance that systems designed for these applications communicate with one another effectively and also offer connectivity and compatibility among different services. This requirement is met only if these systems are designed to conform to International Standards such as JPEG, H.261, HDTV and MPEG. The Discrete Cosine Transform (DCT), Quantization (Q) and Variable Length Coding (VLC) are the basic operations that bring about image compression and are common to all these standards.

The present work proposes new algorithms and schemes for compression of still pictures and video frame sequences and their implementation on Field Programmable Gate Arrays (FPGAs). It can process both monochrome and color images of sizes of up to 1024×768 pixels at 25 frames/second and have enhanced features, namely, automatic image quality control, a novel motion estimation scheme in order to speed up processing and a dynamically reconfigurable video encoder scheme resulting in substantial hardware saving. FPGA has been chosen for the implementation of these schemes since it offers faster design cycle time and are more economical to realize than Application Specific Integrated Circuits (ASIC).

The DCT is computationally very intensive and needs an efficient algorithm and a very large scale integration (VLSI) implementation to achieve real time speeds. This work proposes a new algorithm for processing 2D-DCT and quantization using an FPGA. Its architecture is regular, linear, highly pipelined and enables high speed computation. This work also proposes an effective implementation of VLC for image compression to meet the real time requirements. The scheme has features such as header information and color processing not found in earlier implementations.

A novel scheme is presented to compute energy on-the-fly at the DCT stage and thereby control the quality of the image dynamically. This scheme which uses a concept called pruning increases the processing speed by a factor of two or more when compared to the conventional method of processing without pruning.

A novel block matching algorithm for motion estimation in a video frame sequence, well suited for a high performance FPGA implementation is presented in this work. The algorithm is up to 40% faster when compared to one of the fastest existing algorithms, viz., one-at-a-time step search algorithm without compromising either in the image quality or in the compression effected.

Integrating all the new schemes mentioned earlier, a dynamically reconfigurable scheme for video encoder to switch among many different applications conforming to JPEG, MPEG-1, MPEG-2, and H.263 standards is implemented. The scheme is an efficient and cost-effective solution for video compression as a result of innovative design using well-partitioned algorithms, highly pipelined architecture and coarse-grain parallelism. The reconfiguration time of the video encoder is less than 320 microseconds while switching from one standard to another. This scheme can be easily adapted for a low power design by trading-off power with picture size and system clock frequency.