EE658: VLSI Data Conversion Circuits

• Nagendra Krishnapura
• Shanthi Pavan

• ESB244

A slot(T 12-1, T 4.30-5.30, Th 11-12, Fr 10-11)

• Amrith Sukumaran

There will be assignments approximately every two weeks. These will count for 60% of the grade and the end semester exam for the remaining 40%.

Knowledge of MOS transistor basics related to circuit design, small signal equivalent circuits, small and large signal analysis; Design of building blocks-opamps, bias generators, amplifier stages, basics of continuous-time and discrete-time signals

This course deals with A/D and D/A conversion systems at the block level and some of the building blocks such as the D/A converter and Flash A/D converter at the transistor level.

Topics: Sampling and quantization in time and frequency domains; Reduction of quantization noise by oversampling and noise shaping; Discrete-time and Continuous-time Delta Sigma modulators; Flash A/D converter-Sample and hold circuits, preamplifiers and latches; D/A converter-Current Steering, Resistor array and Switched capacitor array; Static nonidealities of A/D and D/A converters due to component mismatch; Multi step Flash A/D converter;

Lectures recorded in class are available here. Not all lectures are recorded. For topics other than the ones at the link, you can see last year's lectures. You need to register for access.

Assignments will be posted below. You are expected to solve them on your own. You can approach the teaching assistants for clarifications and help. Only electronic submission is allowed. Submissions beyond the due date will receive zero credit. Please Email the assignments ONLY to ee658.iitm@gmail.com

Information on simulators and device models are available here.

• Problem Set 1, due Sept 21
• Problem Set 2, due Sept 14
• Problem Set 3, due Oct. 30: ADC and DAC basics. This assignment needs one of the following files. Use suffix 00, 01, or 02 for roll numbers 3n, 3n+1, 3n+2 respectively. a2dcodes00.txt, a2dcodes01.txt, a2dcodes02.txt
• Problem Set 4, due Nov. 07: ADC and DAC circuit design. This assignment needs the following files. Dout.dat, Idac.dat
• Problem Set 5, due Nov. 30: Single bit CTDSM design.
• Problem Set 6, due Nov. 19: For classroom discussion on Nov. 19th.

ADC and DAC glossary from Maxim.

• A collection of latches from the IEEE Journal of Solid State Circuits. Go through the circuits and see how they work and compare them. Read the authors thought processes in the complete articles.

• C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 184 - 191, February 1990. Discusses latch design, error correction using majority encoding.
• K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit a/d converter in a 0.25-µm digital CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1760 - 1768, December 2000. Discusses bootstrapped sample and hold, interleaved S/H, preamplifiers with offset correction.
• V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, “A Distortion Compensating Flash Analog to Digital Conversion Technique,” IEEE Journal of Solid State Circuits, vol. 41, September 2006. Discusses sample and hold distortion correction, background autozeroing and its effects.

• Douglas Mercer; “A study of error sources in current steering digital-to-analog converters”, 2004 IEEE Custom Integrated Circuits Conference, May 2004. A very good summary of error sources in current steering D/A converters
• Chi-Hung Lin, Klaas Bult; “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998. An extremely well designed DAC which holds its performance up to the nyquist frequency. A very well made DAC IC
• Bernd Schafferer, Richard Adams; “A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications”, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 360 - 361, February 2004. More recent, more resolution; Has techniques to make tail node jumps independent of signal
• Yonghua Cong, Randall L. Geiger; “A 1.5-V 14-bit 100-MS/s self-calibrated DAC”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 2051 - 2060, December 2003. Discusses optimization of switching sequence
• D. Wouter J. Groeneveld, Hans J. Schouwenaars, Henk A. H. Termeer, Cornelis A. A. Bastiaansen; “A self-calibration technique for monolithic high-resolution D/A converters”, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1517 - 1522, December 1989. Calibrated current steering DAC
• Jurgen Deveugele, Michiel Steyaert; “A 10b 250MS/s binary-weighted current-steering DAC”, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 362 - 363, February 2004. Discusses use of full binary weighting as opposed to thermometer MSBs

• Handout on pipelined A/D converters
• J. Mulder, C. M. Ward, C. Lin, D. Kruse, J. R. Westra, M. Lugthart, E. Arslan, R. J. van de Plassche, K. Bult, and F. M. L. van der Goes, “A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 2116 - 2125, December 2004. A very good realization; Also discusses interpolation, offset cancellation, averaging, and pipelining
• S. Lewis et al., “A 10b 20-Msample/s analog-to-digital converter”, IEEE Journal of Solid State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992. One of the first papers discussing 1.5b/stage pipelined conversion
• B. Ginetti and P. Jespers, “A CMOS 13-b cyclic RSD A/D converter” IEEE Journal of Solid State Circuits, vol. 27, no. 7, pp. 957-965, Jul. 1992. One of the first papers discussing 1.5b/stage multi-step conversion

Attendance will be strictly enforced and those falling short will not be permitted to write the end sem exam. If you are more than 5 min. late, please do not enter the classroom.