EE5311: Digital IC Design
Instructors
Schedule
Weekly Quiz
Students will take a quiz on Moodle every week in one of the G slot hours.
Students can contact the TA for questions and doubts in tools and other aspect of the course in one of the G-slot hours.
Evaluation
Assignments:
Weekly Quizzes:
Mid Sem:
End Semester Exam:
Project:
Simulation
Reference Text Books
All lecture notes available here are based on the following text books.
Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India
CMOS VLSI Design, Neil H.E. Weste, David Harris and Ayan Banerjee, 3rd Edition, Pearson Education
Module 6 (Adders and Multipliers) alone uses some extra material from
Learning Objectives
(What the students should be able to do after the course)
Characterize the key delay quantities of a standard cell
Evaluate power dissipated in a circuit (dynamic and leakage)
Design a circuit to perform a certain functionality with specified speed
Identify the critical path of a combinational circuit
Convert the combinational block to pipelined circuit
Calculate the maximum (worst case) operating frequency of the designed circuit
Module-0 - Introduction
Module-1 - The Transistor
Learning Objectives:
Explain short channel effects(SCE) like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, Sub-threshold leakage, Channel length modulation
Derive the equation for ON current of a CMOS transistor with first order SC
Estimate various capacitance values for a transistor
Estimate the equivalent ON resistance of a transistor
Contents:
Silicon and Doping
P-N Junction
CMOS Transistor
Threshold Voltage
ON Current
Channel length modulation
Velocity saturation
Sub-threshold leakage
Drain Induced Barrier Leakage
Gate Induced Drain leakage
(Reverse) Short Channel Effect
Other leakage mechanisms
Capacitance
Resistance
Lecture Slides
Module-2 - Interconnects
Learning Objectives:
Estimate the wire parasitics given the sheet resistance and the capacitance per unit length
Derive the Elmore delay for a given RC tree
Estimate the wire RC delay by applying the Elmore delay model to a distributed RC network
Contents:
Capacitance
Resistance
Sheet Resistance
Skin depth
Resistance Models
Lumped model (C and RC)
Propagating delay and rise time
Elmore delay model
Example - Time constant of a rc-wire model
Lecture Slides
Module-3 - The Inverter
Learning Objectives:
Explain the functioning of a CMOS inverter
Explain the Voltage Transfer Characteristics of an inverter
Derive an expression for the trip point of an inverter
Derive an expression for the delay of an inverter driving a load
Derive expressions for Static, Dynamic and Short Circuit power of an inverter.
Contents:
Switch Model
Transfer Characteristics
Switching Threshold
Noise Margin
Supply Voltage Scaling
Propagation Delay
Power
Dynamic
Short circuit
Leakage
Lecture Slides
Module-4 - Combinational Circuit Design
Learning Objectives:
Explain logical effort (LE) and electrical effort (EE)
Derive the optimum number of buffers with their sizes to drive a load.
Implement any arbitrary boolean function in Static CMOS logic
Derive logical effort for any gate built in any style of logic
Optimize the path delay of arbitrary gates driving a load capacitance
Implement logic functions using ratio'd logic and dynamic logic
Use the pass transistor to implement simple gates like MUX and XORs 8. Explain basic domino logic
Contents:
CMOS gates
Gate sizing
Capacitance estimation
Delay estimation
Logical effort
Path delay optimizaion
Buffer insertion
Circuit Families
Static CMOS
Ratioed gates
Cascode Voltage Switch Logic (CVSL) & Level Translators
Dynamic circuits
Pass Transistor circuits
Lecture Slides
Module-5 - Sequential Circuits
Learning Objectives:
Build elementary sequential circuits like latches and flip flops - Static and Dynamic
Identify devices that affect set up and hold time
Derive max and min delay constraints for latch/ flip flop based pipeline systems
Account for clock skew in a pipelined system
Analyze time borrowing across half cycles and across cycles
Calculate the maximum clock frequency of operation of a pipelined system
Contents:
Sequencing Elements
Sequencing Methods
Flip flop
Latch
Delay definitions
Circuit Implementations of Latch/ Flop
Static
Dynamic
Max delay constraints
Min delay constraints
Time Borrowing
Lecture Slides
Module-6 - Adders and Multipliers
Learning Objectives:
Design a full adder with least PMOS stack size using self duality principle
Construct adder architectures to reduce delay from O(N) to O(\sqrt{N}) - O(log(N))
Draw timing diagrams to show the signal propagation of various adders
Design an array multiplier for both signed and unsigned multiplication
Optimize the arrary multiplier using the inverting property of a Full Adder
Derive the Modified Booth Encoding to reduce the number of partial products
Design and implement a multipler based on the Modified Booth Encoding algorithm
Contents:
Adders
Basic terminology
Full adder circuit design
Inverting Adder
Carry Save Adder
Carry Select Adder
Carry Look Ahead Adder
Multipliers
Basic Terminology
Booth and Modified Booth Encoding
2s Complement Arithmetic
Array Multiplier
Carry Save Multipler
Signed multiplication and carry save implementation
Final Addition
Lecture Slides