===== Development of HDL Cores for FPGA implementation of Demodulator for Satellite data. =====
Reception of voice and image data over satellite requires bandwidths of 64 Kbps or more. Existing scheme for demodulation uses an advanced DSP with a maximum bit rate of 64 Kbps. In order to increase the bandwidth capability, modification of the present scheme using a combination of ADSP and FPGA has been undertaken. \\ 
The work involves development of a new algorithm and its software implementation for validation purposes, investigation of various hardware structures for front end digital filters such as interpolation and Nyquist filters and partitioning of the demodulation scheme into viable modules for DSP and FPGA implementations. Design and integration with the demodulator of a turbo block decoder for forward error correction (FEC) is also envisaged.