^         Project Title  ^  Duration  ^  Total Amount (INR)  ^  Sponsoring Agency  ^  Other faculty members Involved  ^
|Development of the state of the art VLSI design facility \\ [[:people:srini:project:p1|Summary ]]|2 Years  |9 Lakhs  |Ministry of Human Resources Development, Govt. of India  |Dr.K.Radhakrishna Rao,Dr. Vinita Vasudevan, Dr.S.Karmalkar, Dr.R.Sundar, Mr.H.Renganathan|
|Design of Analog and Mixed mode ASICs and Development of Analog ASIC design tools. \\ [[:people:srini:project:p2| Summary  ]]|3 years  |35,58,800/-  |Department of Science & Technology, Govt. of India  |Dr.K.Radhakrishna Rao, Dr.Vinita Vasudevan, Dr.C.Mathiazhagan, Mr.H.Renganathan  |
|Feasibility Studies on Design and Implementation of Basic DSP Building Blocks. \\ [[:people:srini:project:p3|Summary  ]]|30 months  |2,80,000/-  |Indian Space Research Organisation, VSSC, Trivandrum  |Dr.R.Sundar, Mr.H.Renganathan    |
|Special Manpower Development for VLSI Design and Related Software. \\ [[:people:srini:project:p5|Summary  ]]|5 Years  |14.99 Crores ( For 19 Institutions covered by this project)  |Department of Electronics Govt. of India  |Dr.K.Radhakrishna Rao, Dr.Vinita Vasudevan, Dr.R.Sundar, Mr.H.Renganathan  |
|Study of NN-based coding schemes for compression of telemetry data. \\ [[:people:srini:project:p4|Summary  ]]|30 months   |2,80,000/- |Indian Space Research Organisation, VSSC, Trivandrum  |Dr.C.Eswaran, Mr.H.Renganathan  |
|Development of Synthesizable VHDL Cores for DSP. \\ [[:people:srini:project:p9|Summary  ]]|2 Years  |4,89,000/-  |Defense Research and Development Organisation, Govt. of India.  |Dr.Vinita Vasudevan, Mr.H.Renganathan  |
|Design and Implementation of a Multi - FPGA Reconfigurable Processor for Image Compression Applications. \\ [[:people:srini:project:p6|Summary  ]]|2 Years  |6,00,000/-  |Ministry of Human Resources Development, Govt. of India  | Dr.K.Radhakrishna Rao,Dr. Vinita Vasudevan, Mr. H.Renganathan  |
|Development of HDL Cores for FPGA implementation of Demodulator for Satellite data. \\ [[:people:srini:project:p7|Summary  ]]|2 Years  |4,62,000/-  |Indian Space Research Organisation  |Mr. H. Renganathan  |
|Modern design aids for electronic circuits and systems. \\ [[:people:srini:project:p8|Summary  ]]|2 Years  |15,00,000/-  |Ministry of Human Resources Development, Govt. of India  |  |
|Hardware implementation of video imaging system for launch vehicles.\\  [[:people:srini:project:p10|Summary]]  |2 Years  |7,36,000/-  |Indian Space Research Organisation  |Mr. H. Renganathan  |
|Special Manpower Development Programme for VLSI Design and Related Software (SMDP-II)  |5 Years  |49.98 Crores (for 32 Institutions)  |Department of Information Technology, Govt. of India  |Dr. Vinita Vasudevan  |